參數(shù)資料
型號: ST7FLCD1
廠商: 意法半導(dǎo)體
英文描述: 8-bit MCU for LCD Monitors with 60 KBytes Flash, 2 KBytes RAM, 2 DDC Ports and Infrared Controller
中文描述: 8位微控制器的液晶顯示器為60千字節(jié)閃存,2千字節(jié)RAM,2個(gè)DDC的港口和紅外線控制器
文件頁數(shù): 57/95頁
文件大?。?/td> 633K
代理商: ST7FLCD1
57/95
ST7FLCD1
I2C Single-Master Bus Interface
Bit 1 = STOP
Generation of a Stop condition
.
This bit is set and cleared by software. It is also cleared by hardware when the interface is disabled
(PE = 0) or when the Stop condition is sent. In Master mode only:
0
No stop generation
1
Stop generation after the current byte transfer or after the current Start condition is sent.
Bit 0 = ITE
Interrupt enable.
This bit is set and cleared by software and cleared by hardware when the interface is disabled (PE
= 0).
0
Interrupt disabled
1
Interrupt enabled
I2C STATUS REGISTER (I2CSR)
Read Only
Reset Value: 0000 0000 (00h)
Bit 7 = EVF
Event flag.
This bit is set by hardware as soon as an event occurs. It is cleared by software by reading the SR
register in case of error event or as described in
Section 10.5: Transfer Sequencing
. It is also
cleared by hardware when the interface is disabled (PE = 0).
0
No event
1
One of the following events has occurred:
BTF = 1 (Byte received or transmitted)
SB = 1 (Start condition generated)
AF = 1 (No acknowledge received after byte transmission if ACK = 1)
Address byte successfully transmitted.
Bit 6 = AF
Acknowledge Failure.
This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE = 1.
It is cleared by software by reading the SR register or by hardware when the interface is disabled
(PE = 0).
The SCL line is not held low when AF = 1.
0
No acknowledge failure
1
Acknowledge failure
Bit 5 = TRA
Transmitter/Receiver.
When BTF is set, TRA = 1 if a data byte has been transmitted. It is cleared automatically when BTF
is cleared. It is also cleared by hardware when the interface is disabled (PE = 0).
0
Data byte received (if BTF = 1)
1
Data byte transmitted
Bit 4 = Reserved.
Forced to 0 by hardware
.
Bit 3 = BTF
Byte transfer finished.
This bit is set by hardware as soon as a byte is correctly received or transmitted with interrupt
7
6
5
4
3
2
1
0
EVF
AF
TRA
0
BTF
0
M/IDL
SB
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