參數(shù)資料
型號(hào): ST7FLCD1
廠商: 意法半導(dǎo)體
英文描述: 8-bit MCU for LCD Monitors with 60 KBytes Flash, 2 KBytes RAM, 2 DDC Ports and Infrared Controller
中文描述: 8位微控制器的液晶顯示器為60千字節(jié)閃存,2千字節(jié)RAM,2個(gè)DDC的港口和紅外線控制器
文件頁(yè)數(shù): 33/95頁(yè)
文件大?。?/td> 633K
代理商: ST7FLCD1
33/95
ST7FLCD1
Clocks & Low Power Modes
6.2
Power Saving Modes
The MCU offers the possibility to decrease power consumption at any time by software operation.
6.2.1
HALT Mode
HALT mode is the MCU lowest power consumption mode. Also, HALT mode also stops the
oscillator stage completely which is the most critical condition (the MCU cannot recover by itself).
For this reason, HALT mode is not compatible with the watchdog protection.
6.2.2
WAIT Mode
This is a low power consumption mode. The WFI instruction sets the MCU in WAIT mode. The
internal clock remains active but all CPU processing is stopped. However, all other peripherals still
run.
Note:
In WAIT mode, DMA (DDC A and DDC B) accesses are possible.
6.2.3
Exit from HALT and WAIT Modes
The MCU can exit HALT mode upon reception of an external interrupt on pins ITA or ITB. The
oscillator is then turned back on and a stabilizing time is necessary before releasing CPU operation
(4096 CPU clock cycles). After this delay, the CPU continues operation according to the cause of its
release, either by servicing an interrupt or by fetching the reset vector in case of reset.
During WAIT mode, the I bit from the Condition Code register is cleared, enabling all interrupts. This
leads the MCU to exit WAIT mode, the corresponding interrupt vector tois fetched, the interrupt
routine is executed and normal processing resumes.
A reset causes the program counter to fetch the reset vector. Processing starts as with a normal
reset.
Figure 14: Clock System Diagram
Table 8: Watchdog Compatibility
Watchdog
Executing HALT Instruction
Enabled
Generates an immediate reset
Disabled
Puts the MCU in HALT mode
OSC
:3
O
O
f
CPU
and other peripherals
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