參數(shù)資料
型號： ST72F324B
廠商： 意法半導體
英文描述： 5V Range 8-Bit MCU With 8 TO 32K FLASH/ROM, 10-Bit ADC, 4 Timers, SPI, SCI Interface(具有ICP,IAP,Nested Interrupt,TLI,ROP的8位MCU)
中文描述： 5V范圍內(nèi)的8位8到32K閃存/ ROM，10位ADC，4個計時器，SPI和SCI接口（具有比較方案，國際檢察官聯(lián)合會，嵌套中斷，中華語文研習所，人事登記的8位微控制器）
文件頁數(shù)： 70/167頁
文件大?。?/td> 1641K
代理商： ST72F324B
ST72324B
70/167
1
16-BIT TIMER
(Cont’d)
10.3.3.6 Pulse Width Modulation Mode
Pulse Width Modulation (PWM) mode enables the
generation of a signal with a frequency and pulse
length determined by the value of the OC1R and
OC2R registers.
Pulse Width Modulation mode uses the complete
Output Compare 1 function plus the OC2R regis-
ter, and so this functionality can not be used when
PWM mode is activated.
In PWM mode, double buffering is implemented on
the output compare registers. Any new values writ-
ten in the OC1R and OC2R registers are taken
into account only at the end of the PWM period
(OC2) to avoid spikes on the PWM output pin
(OCMP1).
Procedure
To use pulse width modulation mode:
1. Load the OC2R register with the value corre-
sponding to the period of the signal using the
formula in the opposite column.
2. Load the OC1R register with the value corre-
sponding to the period of the pulse if (OLVL1=0
and OLVL2=1) using the formula in the oppo-
site column.
3. Select the following in the CR1 register:
– Using the OLVL1 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with the OC1R register.
– Using the OLVL2 bit, select the level to be ap-
plied to the OCMP1 pin after a successful
comparison with the OC2R register.
4. Select the following in the CR2 register:
– Set OC1E bit: the OCMP1 pin is then dedicat-
ed to the output compare 1 function.
– Set the PWM bit.
– Select the timer clock (CC[1:0]) (see
Table 1
).
If OLVL1=1 and OLVL2=0 the length of the posi-
tive pulse is the difference between the OC2R and
OC1R registers.
If OLVL1=OLVL2 a continuous signal will be seen
on the OCMP1 pin.
The OC
i
R register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
Where:
t
f
CPU
PRESC
= Timer prescaler factor (2, 4 or 8 depend-
ing on CC[1:0] bits, see
Table 1
)
If the timer clock is an external clock the formula is:
= Signal or pulse period (in seconds)
= CPU clock frequency (in hertz)
Where:
t
f
EXT
= Signal or pulse period (in seconds)
= External timer clock frequency (in hertz)
The Output Compare 2 event causes the counter
to be initialized to FFFCh (See
Figure 11
)
Notes:
1. After a write instruction to the OC
i
HR register,
the output compare function is inhibited until the
OC
i
LR register is also written.
2. The OCF1 and OCF2 bits cannot be set by
hardware in PWM mode therefore the Output
Compare interrupt is inhibited.
3. The ICF1 bit is set by hardware when the coun-
ter reaches the OC2R value and can produce a
timer interrupt if the ICIE bit is set and the I bit is
cleared.
4. In PWM mode the ICAP1 pin can not be used
to perform input capture because it is discon-
nected to the timer. The ICAP2 pin can be used
to perform input capture (ICF2 can be set and
IC2R can be loaded) but the user must take
care that the counter is reset each period and
ICF1 can also generates interrupt if ICIE is set.
5. When the Pulse Width Modulation (PWM) and
One Pulse Mode (OPM) bits are both set, the
PWM mode is the only active one.
Counter
= OC1R
OCMP1 = OLVL2
Counter is reset
to FFFCh
Counter
= OC2R
OCMP1 = OLVL1
When
When
Pulse Width Modulation cycle
ICF1 bit is set
OC
i
R Value =
t
*
f
CPU
PRESC
- 5
OC
i
R =
t
*
f
EXT
-5
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