參數(shù)資料
型號： ST72F324B
廠商： 意法半導體
英文描述： 5V Range 8-Bit MCU With 8 TO 32K FLASH/ROM, 10-Bit ADC, 4 Timers, SPI, SCI Interface(具有ICP,IAP,Nested Interrupt,TLI,ROP的8位MCU)
中文描述： 5V范圍內的8位8到32K閃存/ ROM，10位ADC，4個計時器，SPI和SCI接口（具有比較方案，國際檢察官聯(lián)合會，嵌套中斷，中華語文研習所，人事登記的8位微控制器）
文件頁數(shù)： 63/167頁
文件大?。?/td> 1641K
代理商： ST72F324B
ST72324B
63/167
16-BIT TIMER
(Cont’d)
10.3.3.3 Input Capture
In this section, the index,
i
, may be 1 or 2 because
there are 2 input capture functions in the 16-bit
timer.
The two 16-bit input capture registers (IC1R and
IC2R) are used to latch the value of the free run-
ning counter after a transition is detected on the
ICAP
i
pin (see figure 5).
IC
i
R register is a read-only register.
The active transition is software programmable
through the IEDG
i
bit of Control Registers (CR
i
).
Timing resolution is one count of the free running
counter: (
f
CPU
/
CC[1:0]).
Procedure:
To use the input capture function select the follow-
ing in the CR2 register:
– Select the timer clock (CC[1:0]) (see
Table 1
).
– Select the edge of the active transition on the
ICAP2 pin with the IEDG2 bit (the ICAP2 pin
must be configured as floating input or input with
pull-up without interrupt if this configuration is
available).
And select the following in the CR1 register:
– Set the ICIE bit to generate an interrupt after an
input capture coming from either the ICAP1 pin
or the ICAP2 pin
– Select the edge of the active transition on the
ICAP1 pin with the IEDG1 bit (the ICAP1pin must
be configured as floating input or input with pull-
up without interrupt if this configuration is availa-
ble).
When an input capture occurs:
– ICF
i
bit is set.
– The IC
i
R register contains the value of the free
running counter on the active transition on the
ICAP
i
pin (see
Figure 6
).
– A timer interrupt is generated if the ICIE bit is set
and the I bit is cleared in the CC register. Other-
wise, the interrupt remains pending until both
conditions become true.
Clearing the Input Capture interrupt request (i.e.
clearing the ICF
i
bit) is done in two steps:
1. Reading the SR register while the ICF
i
bit is set.
2. An access (read or write) to the IC
i
LR
register.
Notes:
1. After reading the IC
i
HR register, transfer of
input capture data is inhibited and ICF
i
will
never be set until the IC
i
LR register is also
read.
2. The IC
i
R register contains the free running
counter value which corresponds to the most
recent input capture.
3. The 2 input capture functions can be used
together even if the timer also uses the 2 output
compare functions.
4. In One pulse Mode and PWM mode only Input
Capture 2 can be used.
5. The alternate inputs (ICAP1 & ICAP2) are
always directly connected to the timer. So any
transitions on these pins activates the input
capture function.
Moreover if one of the ICAP
i
pins is configured
as an input and the second one as an output,
an interrupt can be generated if the user tog-
gles the output pin and if the ICIE bit is set.
This can be avoided if the input capture func-
tion
i
is disabled by reading the IC
i
HR (see note
1).
6. The TOF bit can be used with interrupt genera-
tion in order to measure events that go beyond
the timer range (FFFFh).
MS Byte
IC
i
HR
LS Byte
IC
i
LR
ICiR
1
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