參數(shù)資料
型號： ST72F324B
廠商： 意法半導體
英文描述： 5V Range 8-Bit MCU With 8 TO 32K FLASH/ROM, 10-Bit ADC, 4 Timers, SPI, SCI Interface(具有ICP,IAP,Nested Interrupt,TLI,ROP的8位MCU)
中文描述： 5V范圍內(nèi)的8位8到32K閃存/ ROM，10位ADC，4個計時器，SPI和SCI接口（具有比較方案，國際檢察官聯(lián)合會，嵌套中斷，中華語文研習所，人事登記的8位微控制器）
文件頁數(shù)： 43/167頁
文件大?。?/td> 1641K
代理商： ST72F324B
ST72324B
43/167
POWER SAVING MODES
(Cont’d)
8.4.2 HALT MODE
The HALT mode is the lowest power consumption
mode of the MCU. It is entered by executing the
‘HALT’ instruction when the OIE bit of the Main
Clock Controller Status register (MCCSR) is
cleared (see
Section 10.2 on page 56
for more de-
tails on the MCCSR register).
The MCU can exit HALT mode on reception of ei-
ther a specific interrupt (see
Table 8, “Interrupt
Mapping,” on page 36
) or a RESET. When exiting
HALT mode by means of a RESET or an interrupt,
the oscillator is immediately turned on and the 256
or 4096 CPU cycle delay is used to stabilize the
oscillator. After the start up delay, the CPU
resumes operation by servicing the interrupt or by
fetching the reset vector which woke it up (see
Fig-
ure 28
).
When entering HALT mode, the I[1:0] bits in the
CC register are forced to ‘10b’to enable interrupts.
Therefore, if an interrupt is pending, the MCU
wakes up immediately.
In HALT mode, the main oscillator is turned off
causing all internal processing to be stopped, in-
cluding the operation of the on-chip peripherals.
All peripherals are not clocked except the ones
which get their clock supply from another clock
generator (such as an external or auxiliary oscilla-
tor).
The compatibility of Watchdog operation with
HALT mode is configured by the “WDGHALT” op-
tion bit of the option byte. The HALT instruction
when executed while the Watchdog system is en-
abled, can generate a Watchdog RESET (see
Section 14.1 on page 151
) for more details.
Figure 27. HALT Timing Overview
Figure 28. HALT Mode Flow-chart
Notes:
1. WDGHALT is an option bit. See option byte sec-
tion for more details.
2. Peripheral clocked with an external clock source
can still be active.
3. Only some specific interrupts can exit the MCU
from HALT mode (such as external interrupt). Re-
fer to
Table 8, “Interrupt Mapping,” on page 36
for
more details.
4. Before servicing an interrupt, the CC register is
pushed on the stack. The I[1:0] bits of the CC reg-
ister are set to the current software priority level of
the interrupt routine and recovered when the CC
register is popped.
HALT
RUN
RUN
256 OR 4096 CPU
CYCLE DELAY
RESET
OR
INTERRUPT
HALT
INSTRUCTION
[MCCSR.OIE=0]
FETCH
VECTOR
HALT
INSTRUCTION
(MCCSR.OIE=0)
RESET
INTERRUPT
3)
Y
N
N
Y
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
2)
OFF
OFF
OFF
10
FETCH RESET VECTOR
OR SERVICE INTERRUPT
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
ON
OFF
ON
XX
4)
CPU
I[1:0] BITS
OSCILLATOR
PERIPHERALS
ON
ON
ON
XX
4)
256 OR 4096 CPU CLOCK
CYCLE
DELAY
WATCHDOG
ENABLE
DISABLE
WDGHALT
1)
0
WATCHDOG
RESET
1
1
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