參數(shù)資料
型號(hào): ST72F324B
廠商: 意法半導(dǎo)體
英文描述: 5V Range 8-Bit MCU With 8 TO 32K FLASH/ROM, 10-Bit ADC, 4 Timers, SPI, SCI Interface(具有ICP,IAP,Nested Interrupt,TLI,ROP的8位MCU)
中文描述: 5V范圍內(nèi)的8位8到32K閃存/ ROM,10位ADC,4個(gè)計(jì)時(shí)器,SPI和SCI接口(具有比較方案,國(guó)際檢察官聯(lián)合會(huì),嵌套中斷,中華語文研習(xí)所,人事登記的8位微控制器)
文件頁數(shù): 23/167頁
文件大?。?/td> 1641K
代理商: ST72F324B
ST72324B
23/167
6 SUPPLY, RESET AND CLOCK MANAGEMENT
The device includes a range of utility features for
securing the application in critical situations (for
example in case of a power brown-out), and re-
ducing the number of external components. An
overview is shown in
Figure 11
.
For more details, refer to dedicated parametric
section.
Main features
Optional PLL for multiplying the frequency by 2
(not to be used with internal RC oscillator in
order to respect the max. operating frequency)
Reset Sequence Manager (RSM)
Multi-Oscillator Clock Management (MO)
– 5 Crystal/Ceramic resonator oscillators
– 1 Internal RC oscillator
System Integrity Management (SI)
– Main supply Low voltage detection (LVD)
– Auxiliary Voltage detector (AVD) with interrupt
capability for monitoring the main supply
6.1 PHASE LOCKED LOOP
If the clock frequency input to the PLL is in the
range 2 to 4 MHz, the PLL can be used to multiply
the frequency by two to obtain an f
OSC2
of 4 to 8
MHz. The PLL is enabled by option byte. If the PLL
is disabled, then f
OSC2 =
f
OSC
/2.
Caution:
The PLL is not recommended for appli-
cations where timing accuracy is required.
Caution
: The PLL must not be used with the inter-
nal RC oscillator.
Figure 10. PLL Block Diagram
Figure 11. Clock, Reset and Supply Block Diagram
0
1
PLL OPTION BIT
PLL x 2
f
OSC2
/ 2
f
OSC
LOW VOLTAGE
DETECTOR
(LVD)
f
OSC2
AUXILIARY VOLTAGE
DETECTOR
(AVD)
MULTI-
OSCILLATOR
(MO)
OSC1
RESET
V
SS
V
DD
RESET SEQUENCE
MANAGER
(RSM)
OSC2
MAIN CLOCK
CONTROLLER
WITH REALTIME
CLOCK (MCC/RTC)
AVD Interrupt Request
PLL
(option)
SYSTEM INTEGRITY MANAGEMENT
WATCHDOG
SICSR
TIMER (WDG)
AVD AVD LVD
IE
F
RF
WDG
RF
f
OSC
0
f
CPU
0
0
0
1
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