參數(shù)資料
型號: ST72F324B
廠商: 意法半導(dǎo)體
英文描述: 5V Range 8-Bit MCU With 8 TO 32K FLASH/ROM, 10-Bit ADC, 4 Timers, SPI, SCI Interface(具有ICP,IAP,Nested Interrupt,TLI,ROP的8位MCU)
中文描述: 5V范圍內(nèi)的8位8到32K閃存/ ROM,10位ADC,4個計時器,SPI和SCI接口(具有比較方案,國際檢察官聯(lián)合會,嵌套中斷,中華語文研習(xí)所,人事登記的8位微控制器)
文件頁數(shù): 163/167頁
文件大?。?/td> 1641K
代理商: ST72F324B
ST72324B
163/167
.ext1_rt
LD A,#00
LD sema,A
IRET
Case 2:
Writing to PxOR or PxDDR with Global In-
terrupts Disabled:
SIM
; set the interrupt mask
LD A,PFDR
AND A,#$02
LD X,A
; store the level before writing to
PxOR/PxDDR
LD A,#$90
LD PFDDR,A; Write into PFDDR
LD A,#$ff
LD PFOR,A ; Write to PFOR
LD A,PFDR
AND A,#$02
LD Y,A
; store the level after writing to PxOR/
PxDDR
LD A,X
; check for falling edge
cp A,#$02
jrne OUT
TNZ Y
jrne OUT
LD A,#$01
LD sema,A ; set the semaphore to '1' if edge is
detected
RIM
; reset the interrupt mask
LD A,sema ; check the semaphore status
CP A,#$01
jrne OUT
call call_routine; call the interrupt routine
RIM
OUT:
RIM
JP while_loop
.call_routine ; entry to call_routine
PUSH A
PUSH X
PUSH CC
.ext1_rt
; entry to interrupt routine
LD A,#$00
LD sema,A
IRET
; entry to interrupt routine
15.1.3 Unexpected Reset Fetch
If an interrupt request occurs while a "POP CC" in-
struction is executed, the interrupt controller does
not recognise the source of the interrupt and, by
default, passes the RESET vector address to the
CPU.
Workaround
To solve this issue, a "POP CC" instruction must
always be preceded by a "SIM" instruction.
15.1.4 Clearing active interrupts outside
interrupt routine
When an active interrupt request occurs at the
same time as the related flag is being cleared, an
unwanted reset may occur.
Note:
clearing the related interrupt mask will not
generate an unwanted reset
Concurrent interrupt context
The symptom does not occur when the interrupts
are handled normally, i.e.
when:
– The interrupt flag is cleared within its own inter-
rupt routine
– The interrupt flag is cleared within any interrupt
routine
– The interrupt flag is cleared in any part of the
code while this interrupt is disabled
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
Perform SIM and RIM operation before and after
resetting an active interrupt request.
Example:
SIM
reset interrupt flag
RIM
Nested interrupt context:
The symptom does not occur when the interrupts
are handled normally, i.e.
when:
– The interrupt flag is cleared within its own inter-
rupt routine
– The interrupt flag is cleared within any interrupt
routine with higher or identical priority level
– The interrupt flag is cleared in any part of the
code while this interrupt is disabled
If these conditions are not met, the symptom can
be avoided by implementing the following se-
quence:
1
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