參數(shù)資料
型號： ST72F324B
廠商： 意法半導(dǎo)體
英文描述： 5V Range 8-Bit MCU With 8 TO 32K FLASH/ROM, 10-Bit ADC, 4 Timers, SPI, SCI Interface(具有ICP,IAP,Nested Interrupt,TLI,ROP的8位MCU)
中文描述： 5V范圍內(nèi)的8位8到32K閃存/ ROM，10位ADC，4個計時器，SPI和SCI接口（具有比較方案，國際檢察官聯(lián)合會，嵌套中斷，中華語文研習(xí)所，人事登記的8位微控制器）
文件頁數(shù)： 65/167頁
文件大小： 1641K
代理商： ST72F324B
ST72324B
65/167
16-BIT TIMER
(Cont’d)
10.3.3.4 Output Compare
In this section, the index,
i
, may be 1 or 2 because
there are 2 output compare functions in the 16-bit
timer.
This function can be used to control an output
waveform or indicate when a period of time has
elapsed.
When a match is found between the Output Com-
pare register and the free running counter, the out-
put compare function:
– Assigns pins with a programmable value if the
OC
i
E bit is set
– Sets a flag in the status register
– Generates an interrupt if enabled
Two 16-bit registers Output Compare Register 1
(OC1R) and Output Compare Register 2 (OC2R)
contain the value to be compared to the counter
register each timer clock cycle.
These registers are readable and writable and are
not affected by the timer hardware. A reset event
changes the OC
i
R value to 8000h.
Timing resolution is one count of the free running
counter: (
f
CPU/
CC[1:0]
).
Procedure:
To use the output compare function, select the fol-
lowing in the CR2 register:
– Set the OC
i
E bit if an output is needed then the
OCMP
i
pin is dedicated to the output compare
i
signal.
– Select the timer clock (CC[1:0]) (see
Table 1
).
And select the following in the CR1 register:
– Select the OLVL
i
bit to applied to the OCMP
i
pins
after the match occurs.
– Set the OCIE bit to generate an interrupt if it is
needed.
When a match is found between OCRi register
and CR register:
– OCF
i
bit is set.
– The OCMP
i
pin takes OLVL
i
bit value (OCMP
i
pin latch is forced low during reset).
– A timer interrupt is generated if the OCIE bit is
set in the CR1 register and the I bit is cleared in
the CC register (CC).
The OC
i
R register value required for a specific tim-
ing application can be calculated using the follow-
ing formula:
Where:
t
f
CPU
PRESC
= Timer prescaler factor (2, 4 or 8 de-
pending on CC[1:0] bits, see
Table 1
)
= Output compare period (in seconds)
= CPU clock frequency (in hertz)
If the timer clock is an external clock, the formula
is:
OC
i
R =
t
*
f
EXT
Where:
t
f
EXT
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
Clearing the output compare interrupt request (i.e.
clearing the OCF
i
bit) is done by:
1. Reading the SR register while the OCF
i
bit is
set.
2. An access (read or write) to the OC
i
LR register.
The following procedure is recommended to pre-
vent the OCF
i
bit from being set between the time
it is read and the write to the OC
i
R
register:
– Write to the OC
i
HR register (further compares
are inhibited).
– Read the SR register (first step of the clearance
of the OCF
i
bit, which may be already set).
– Write to the OC
i
LR register (enables the output
compare function and clears the OCF
i
bit).
MS Byte
OC
i
HR
LS Byte
OC
i
LR
OC
i
R
OC
i
R =
t
*
f
CPU
PRESC
1
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