參數(shù)資料
型號： ST72F324B
廠商： 意法半導(dǎo)體
英文描述： 5V Range 8-Bit MCU With 8 TO 32K FLASH/ROM, 10-Bit ADC, 4 Timers, SPI, SCI Interface(具有ICP,IAP,Nested Interrupt,TLI,ROP的8位MCU)
中文描述： 5V范圍內(nèi)的8位8到32K閃存/ ROM，10位ADC，4個計時器，SPI和SCI接口（具有比較方案，國際檢察官聯(lián)合會，嵌套中斷，中華語文研習(xí)所，人事登記的8位微控制器）
文件頁數(shù)： 138/167頁
文件大?。?/td> 1641K
代理商： ST72F324B
ST72324B
138/167
1
CONTROL PIN CHARACTERISTICS
(Cont’d)
Figure 74. RESET
pin
protection
when LVD is enabled.
1)2)
Figure 75. RESET pin
protection
when LVD is disabled.
1)
Note 1:
1.1 The reset network protects the device against parasitic resets.
1.2 The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the
device can be damaged when the ST7 generates an internal reset (LVD or watchdog).
1.3 Whatever the reset source is (internal or external), the user must ensure that the level on the RESET pin can go below
the V
IL
max. level specified in
Section 12.10.1
. Otherwise the reset will not be taken into account internally.
1.4 Because the reset circuit is designed to allow the internal RESET to be output in the RESET pin, the user must ensure
that the current sunk on the RESET pin (by an external pull-up for example) is less than the absolute maximum value
specified for I
INJ(RESET)
in
Section 12.2.2 on page 116
.
Note 2:
2.1 When the LVD is enabled, it is mandatory not to connect a pull-up resistor. A 10nF pull-down capacitor is recommend-
ed to filter noise on the reset line.
2.2. In case a capacitive power supply is used, it is recommended to connect a1MW pull-down resistor to the RESET pin
to discharge any residual voltage induced by this capacitive power supply (this will add 5μA to the power consumption of
the MCU).
2.3. Tips when using the LVD:
– 1. Check that all recommendations related to reset circuit have been applied (see notes above)
– 2. Check that the power supply is properly decoupled (100nF + 10μF close to the MCU). Refer to AN1709. If this
cannot be done, it is recommended to put a 100nF + 1MW pull-down on the RESET pin.
– 3. The capacitors connected on the RESET pin and also the power supply are key to avoiding any start-up margin-
ality. In most cases, steps 1 and 2 above are sufficient for a robust solution. Otherwise: replace 10nF pull-down on
the RESET pin with a 5μF to 20μF capacitor.”
0.01
μ
F
ST72XXX
PULSE
GENERATOR
Filter
R
ON
V
DD
WATCHDOG
LVD RESET
INTERNAL
RESET
RESET
EXTERNAL
Recommended
1M
Optional
(note 2.2)
0.01
μ
F
V
DD
0.01
μ
F
EXTERNAL
RESET
CIRCUIT
USER
V
DD
4.7k
Required
Recommended
ST72XXX
PULSE
GENERATOR
Filter
R
ON
V
DD
WATCHDOG
INTERNAL
RESET
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參數(shù)描述
ST72F324BJ2B6 功能描述:8位微控制器 -MCU ST72324B 5V RANGE 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST72F324BJ2T6 功能描述:8位微控制器 -MCU 8-BIT MCU W/ 8-32K Flash/ROM ADC RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST72F324BJ4B5 功能描述:8位微控制器 -MCU ST72324B 5V RANGE 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST72F324BJ4B6 功能描述:8位微控制器 -MCU 5V RANGE 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
ST72F324BJ4T3 功能描述:8位微控制器 -MCU ST72324B 5V RANGE 8B MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數(shù)據(jù)總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風(fēng)格:SMD/SMT
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