參數(shù)資料
型號： ST72F324B
廠商： 意法半導體
英文描述： 5V Range 8-Bit MCU With 8 TO 32K FLASH/ROM, 10-Bit ADC, 4 Timers, SPI, SCI Interface(具有ICP,IAP,Nested Interrupt,TLI,ROP的8位MCU)
中文描述： 5V范圍內的8位8到32K閃存/ ROM，10位ADC，4個計時器，SPI和SCI接口（具有比較方案，國際檢察官聯(lián)合會，嵌套中斷，中華語文研習所，人事登記的8位微控制器）
文件頁數(shù)： 51/167頁
文件大小： 1641K
代理商： ST72F324B
ST72324B
51/167
10 ON-CHIP PERIPHERALS
10.1 WATCHDOG TIMER (WDG)
10.1.1 Introduction
The Watchdog timer is used to detect the occur-
rence of a software fault, usually generated by ex-
ternal interference or by unforeseen logical condi-
tions, which causes the application program to
abandon its normal sequence. The Watchdog cir-
cuit generates an MCU reset on expiry of a pro-
grammed time period, unless the program refresh-
es the counter’s contents before the T6 bit be-
comes cleared.
10.1.2 Main Features
■
Programmable free-running downcounter
■
Programmable reset
■
Reset (if watchdog activated) when the T6 bit
reaches zero
■
Optional
reset
on
(configurable by option byte)
■
Hardware Watchdog selectable by option byte
HALT
instruction
10.1.3 Functional Description
The counter value stored in the Watchdog Control
register (WDGCR bits T[6:0]), is decremented
every 16384 f
OSC2
cycles (approx.), and the
length of the timeout period can be programmed
by the user in 64 increments.
If the watchdog is activated (the WDGA bit is set)
and when the 7-bit timer (bits T[6:0]) rolls over
from 40h to 3Fh (T6 becomes cleared), it initiates
a reset cycle pulling low the reset pin for typically
500ns.
The application program must write in the
WDGCR register at regular intervals during normal
operation to prevent an MCU reset. This down-
counter is free-running: it counts down even if the
watchdog is disabled. The value to be stored in the
WDGCR register must be between FFh and C0h:
– The WDGA bit is set (watchdog enabled)
– The T6 bit is set to prevent generating an imme-
diate reset
– The T[5:0] bits contain the number of increments
which represents the time delay before the
watchdog produces a reset (see
Figure 32. Ap-
proximate Timeout Duration
). The timing varies
between a minimum and a maximum value due
to the unknown status of the prescaler when writ-
ing to the WDGCR register (see
Figure 33
).
Following a reset, the watchdog is disabled. Once
activated it cannot be disabled, except by a reset.
The T6 bit can be used to generate a software re-
set (the WDGA bit is set and the T6 bit is cleared).
If the watchdog is activated, the HALT instruction
will generate a Reset.
Figure 31. Watchdog Block Diagram
RESET
WDGA
6-BIT DOWNCOUNTER (CNT)
f
OSC2
T6
T0
WDG PRESCALER
DIV 4
WATCHDOG CONTROL REGISTER (WDGCR)
T1
T2
T3
T4
T5
12-BIT MCC
RTC COUNTER
MSB
LSB
DIV 64
0
5
6
11
MCC/RTC
TB[1:0] bits
(MCCSR
Register)
1
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