參數(shù)資料
型號: ST72F324B
廠商: 意法半導(dǎo)體
英文描述: 5V Range 8-Bit MCU With 8 TO 32K FLASH/ROM, 10-Bit ADC, 4 Timers, SPI, SCI Interface(具有ICP,IAP,Nested Interrupt,TLI,ROP的8位MCU)
中文描述: 5V范圍內(nèi)的8位8到32K閃存/ ROM,10位ADC,4個(gè)計(jì)時(shí)器,SPI和SCI接口(具有比較方案,國際檢察官聯(lián)合會,嵌套中斷,中華語文研習(xí)所,人事登記的8位微控制器)
文件頁數(shù): 137/167頁
文件大小: 1641K
代理商: ST72F324B
ST72324B
137/167
12.10 CONTROL PIN CHARACTERISTICS
12.10.1 Asynchronous RESET Pin
Subject to general operating conditions for V
DD
, f
CPU
, and T
A
unless otherwise specified.
Notes:
1. Data based on characterization results, not tested in production.
2.
Hysteresis voltage between Schmitt trigger switching levels.
3. The I
current sunk must always respect the absolute maximum rating specified in
Section 12.2.2
and the sum of I
IO
(I/O ports and control pins) must not exceed I
VSS
.
4. To guarantee the reset of the device, a minimum pulse has to be applied to the RESET pin. All short pulses applied on
the RESET pin with a duration below t
h(RSTL)in
can be ignored.
5. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in noisy en-
vironments.
6. Data guaranteed by design, not tested in production.
Symbol
V
IL
V
IH
V
hys
V
OL
I
IO
R
ON
t
w(RSTL)out
Generated reset pulse duration
t
h(RSTL)in
t
g(RSTL)in
Parameter
Conditions
Min
Typ
Max
0.3xV
DD
Unit
V
Input low level voltage
1)
Input high level voltage
1)
Schmitt trigger voltage hysteresis
2)
Output low level voltage
3)
Driving current on RESET pin
Weak pull-up equivalent resistor
0.7xV
DD
2.5
0.2
2
30
30
V
DD
=5V
I
IO
=+2mA
0.5
V
mA
k
μ
s
μ
s
ns
V
DD
=5V
Internal reset sources
20
20
2.5
120
42
6)
External reset pulse hold time
4)
Filtered glitch duration
5)
200
1
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