參數(shù)資料
型號(hào): SSTE32882HLBBKG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時(shí)鐘及定時(shí)
英文描述: SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝: 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁(yè)數(shù): 57/69頁(yè)
文件大?。?/td> 1263K
代理商: SSTE32882HLBBKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
60
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Test Circuits and Switching Waveforms
Parameter Measurement Information
All input pulses are supplied by generators having the following characteristics: 300MHz
≤ PRR ≤ 810 MHz;
Zo = 50
Ω; input slew rate = 1 V/ns ± 20%, unless otherwise specified. The outputs are measured one at a time with
one transition per measurement.
Qn and Yn Load circuit for propagation delay and slew measurement
1 CL is parasitic (probe and jig capacitance).
Voltage waveforms; propagation delay times
VTT = VDD/2
VICR Cross Point Voltage
VI(P-P) = 500mV (1.5V operation) or 450mV (1.35V operation)
tPDM1, tPDM2 the larger number of both has to be taken when performing tPDM max measurement, the smaller
number of both has to be taken when performing tPDM min measurement.
CL<2.5pF(1)
DUT
OUT
Test point
CK Inputs
TL = 50
Ω
RL = 100
Ω
Test point
VTT
RL=50
Ω
CK
Trace delay matched on load board
VTT
Q Output
VTT
CK
tPDM1tPDM2
VICR
VI(P-P)
相關(guān)PDF資料
PDF描述
SSTUA32864EC,557 SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96
SSTUA32866EC/G 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
SSTUA32866EC,557 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
SSTUA32866EC/G,551 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
SSTUA32866EC/G,557 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SSTE32882HLBBKG8 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER
SSTE32882KA1AKG 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882KA1AKG8 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882KA1AKG8/M 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel
SSTE32882TNA1AKG8 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel