參數(shù)資料
型號： SSTE32882HLBBKG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時鐘及定時
英文描述： SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝： 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁數(shù)： 29/69頁
文件大?。?/td> 1263K
代理商： SSTE32882HLBBKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
35
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Timing of clock, data and parity signals
1 CK left out for better visibility.
The next figure shows the parity diagram with two consecutive parity-error occurrences and assumes the
occurrence of both parity errors when data is clocked in at the n and n+1 input clock cycles (PAR_IN clocked in on
the n+1 and n+2 input clock cycles).
Two Consecutive Parity-Error Occurrences
1 CK left out for better visibility.
The next figure shows the parity diagram with two parity-error occurrences separated by a clock cycle with no error
occurrence. The diagram assumes the occurrence of two parity errors when data is clocked in at the n and n+2
input clock cycles (PAR_IN clocked in on the n+1 and n+3 input clock cycles).
Two Parity-Error Occurrences Separated by a Clock Cycle of no Error Occurrence
1 CK left out for better visibility.
The next figure shows the parity diagram with two parity-error occurrences separated by two input clock cycles with
no error occurrence. The diagram assumes the occurrence of two parity errors when data is clocked in at the n and
n+3 input clock cycles (PAR_IN clocked in on the n+1 and n+4 input clock cycles).
CK(1)
CA
Input
PAR_IN
CA0
P0
CA1
P1
CA2
P2
ERROUT
nn+1
n+2n+3
n+4n+5
n+6
ERROUT resulting from CA0 - P0
CK(1)
CA
Input
PAR_IN
CA0
P0
CA1
P1
CA2
P2
ERROUT
nn+1
n+2n+3
n+4n+5
n+6
ERROUT resulting from CA0 - P0, followed by 2nd error in CA1 - P1
CK(1)
CA
Input
PAR_IN
CA0
P0
CA1
P1
CA2
P2
ERROUT
n
n+1
n+2
n+3
n+4
n+5
n+6
ERROUT resulting from CA0 - P0, followed by 2nd error in CA2 - P2
n+7
n+8
n+9
CA3
P3
P4
CA4
CA5
P5
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相關代理商/技術參數(shù)
參數(shù)描述
SSTE32882HLBBKG8 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER
SSTE32882KA1AKG 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882KA1AKG8 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882KA1AKG8/M 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel
SSTE32882TNA1AKG8 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel
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