參數(shù)資料
型號(hào): SSTE32882HLBBKG
廠(chǎng)商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類(lèi): 時(shí)鐘及定時(shí)
英文描述: SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝: 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁(yè)數(shù): 13/69頁(yè)
文件大小: 1263K
代理商: SSTE32882HLBBKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
20
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Capacitance Values
Symbol
Parameter
Conditions
DDR3/DDR3L
800/1066/1333/1600
DDR3-1866
Unit
Min
Typ
Max
Min
Typ
Max
CI
Input capacitance, Data inputs
see footnote1,2
1 This parameter is not subject to production test. It is verified by design and characterization. Input capacitance is measured according to JEP147 ("PROCEDURE
FOR MEASURING INPUT CAPACITANCE USING A VECTOR NETWORK ANALYZER (VNA)") with VDD, VSS, AVDD, AVSS, PVDD, PVSS, VREF applied
and all other pins (except the pin under test) floating. Input capacitance are measured with the device default settings when MIRROR=Low.
2. Data Inputs are DCKE0/1, DODT0/1, DA0..DA15, DBA0..DBA2, DRAS, DWE, PAR_IN, DCS[1:0], when QCSEN = HIGH, DCS[3:0] when QCSEN =LO
1.5
-
2.5
1.5
-
2.2
pF
Input capacitance, CK, CK, FBIN, FBIN‘
see footnote1
1.5
-
2.5
1.5
-
2.2
pF
CO
Output capacitance, Re-driven and Clock
Outputs
QxA0..QxA15, QxBA0..QxBA2, QxCS0/1,
QxCKE0/1, QxODT0/1, QxRAS, QxCAS,
QxWE, Y0, Y0.. Y3, Y3
1-
2
pF
C
Delta capacitance over all inputs
-
0.5
-
0.5
pF
CIR
Input capacitance, RESET, MIRROR,
QCSEN
VI =VDD or GND; VDD = 1.5 V
--
3
-
3
pF
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