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參數(shù)資料
| 型號： | SSTE32882HLBBKG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘及定時 |
| 英文描述： | SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176 |
| 封裝： | 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176 |
| 文件頁數(shù)： | 21/69頁 |
| 文件大小： | 1263K |
| 代理商： | SSTE32882HLBBKG |
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1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
28
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
1. This skew represents the absolute output clock skew and contains the pad skew and package skew (See “Clock Output (Yn)
Skew”). This parameter is specified for the clock pairs on each side of the register independently. The skew is applicable to left
side clock pairs between Y0/Y0 and Y2/Y2, as well as right side of the clock pairs between Y1/Y1 and Y3/Y3. This is not a tested
parameter and has to be considered as a design goal only.
2. This skew represents the absolute Qn skew compared to the output clock (Yn), and contains the register pad skew, clock
skew and package routing skew (See “Qn Output Skew for Standard 1/2-Clock Pre-Launch”). The output clock jitter is not
included in this skew. The Qn output can either be early or late. This parameter applies to each side of the register
independently. The parameter includes the skew related to simultaneous switching noise (SSO).
3. The parameter is a measure of the output clock pulse width HIGH/LOW. The output clock duty cycle can be calculated based
on tPW.
4. This skew represents the absolute Qn skew compared to the output clock (Yn), and contains the register pad skew, clock
skew and package routing skew (See “Qn Output Skew for Standard 3/4-Clock Pre-Launch”). The output clock jitter is not
included in this skew. The Qn output can either be early or late. This parameter applies to each side of the register
independently. The parameter includes the skew related to simultaneous switching noise (SSO).
5. This parameter measures the delay from the rising differential input clock which samples incoming C/A to the rising differential
output clock that will be used to sample the same C/A data. tSTAOFF may vary by the amount of tDYNOFF based on voltage and
temperature drift as well as tracking error and jitter. Including this variation tSTAOFF may not exceed the limits set by tSTAOFF(MIN)
and tSTAOFF(MAX).
6. See “Measurement Requirement for tSTAOFF and tDYNOFF“.
7. Implies a -3 dB bandwidth and jitter peaking of 3 dB.
Clock Output (Yn) Skew
tDYNOFF6
Maximum variation in
delay between the
input & output clock
-
160
-
130
-
110
-
90
-
70
ps
SSC modulation
frequency
30
33
30
33
30
33
30
33
kHz
SSC clock input
frequency deviation
0.00
-0.5
0.00
-0.5
0.00
-0.5
0.00
-0.5
0.00
-0.5
%
tBAND
PLL Loop bandwidth
(-3 dB from unity gain)
257
307
357
407
-457
-MHz
Symbol
Parameter
Conditions
DDR3/
DDR3-800
DDR3/
DDR3L-1066
DDR3/
DDR3L-1333
DDR3/
DDR3L-1600
DDR3-1866
Unit
tCK
tCKSK
Y0
Y2
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SSTE32882HLBBKG8 | 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER |
| SSTE32882KA1AKG | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTE32882KA1AKG8 | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時鐘頻率:36 MHz 傳播延遲時間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTE32882KA1AKG8/M | 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel |
| SSTE32882TNA1AKG8 | 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel |
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