參數(shù)資料
型號： SSTE32882HLBBKG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝： 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁數(shù)： 54/69頁
文件大?。?/td> 1263K
代理商： SSTE32882HLBBKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
58
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
RC9: Power Saving Settings Control Word
The SSTE32882KA1 features a weak drive mode, which is a variant of the floating mode set in RC0. If Bit DA4 of
RC0 is set to ‘1’, then Bit DA3 of RC9 selects between floating mode and weak drive mode.
The SSTE32882KA1 register supports different power down modes. By default, the Power Down feature is
disabled (RC9[DBA1]=0). The register ignores CKE Power Down mode setting when this function is disabled. If
the CKE Power Down mode is enabled (RC9[DBA1]=1), then power down is invoked once both DCKE0 and
DCKE1 are low. Bit DBA0 selects how IBT and ODT behaves.
RC10: Encoding for RDIMM Operating Speed
The encoding value is used to inform the register the operating speed that it is being run at in a system. It is not an indicator
of how fast or slow a register can run
Input
Definition
Encoding
DBA1
DBA0
DA4
DA3
xx
x
0
Weak Drive Mode
Floating
xx
x
1
Typical weak drive enabled1
Weak Driver Impedance:
70
Ω (min), 100Ω (nom), 120Ω (min)
1
To get optimum power saving while keeping the VIL DC (max) limit for SDRAM, the Weak Drive Mode Im-
pedance should be 70Ω (min), 100Ω (nom), 120Ω (min).
xx
0
x
Reserved
xx
1
x
Reserved
10
x
CKE Power Down Mode
CKE power down with IBT ON, QxODT is a
function of DxODT
1
x
CKE power down with IBT off, QxODT held LOW
0x
x
CKE Power Down Mode
Enable
Disabled
1x
x
Enabled
Input
Definition
Encoding
DBA1
DBA0
DA4
DA3
x
000
f < 800 MTS
DDR3-800 (default)
x
001
800 MTS < f < 1066 MTS
DDR3-1066
x
0
1
0
1066 MTS < f < 1333 MTS
DDR3-1333
x
0
1
1333 MTS < f < 1600 MTS
DDR3-1600
x
1
0
1600 MTS < f < 1866 MTS
DDR3-1866
x
1
0
1
Reserved
x
1
0
Reserved
x
1
Reserved
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SSTE32882HLBBKG8 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER
SSTE32882KA1AKG 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882KA1AKG8 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882KA1AKG8/M 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel
SSTE32882TNA1AKG8 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel
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