參數(shù)資料
型號(hào)： SSTE32882HLBBKG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝： 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁數(shù)： 32/69頁
文件大?。?/td> 1263K
代理商： SSTE32882HLBBKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
38
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
REGISTER CKE POWER DOWN WITH IBT OFF
Upon entry into CKE Power Down mode with IBT off, all register input buffers including IBT are disabled except for
CK/CK, DCKEn, FBIN/FBIN, and RESET. The SSTE32882KA1 disables input buffers within tInDIS clocks after
latching both DCKEn Low. In order to eliminate and false parity check error, the PAR_IN input buffer has to be kept
active for 1 tCK after Address and Command input buffers disabled. After tInDIS, the register can tolerate floating
input except for CK/CK, DCKEn and RESET. The SSTE32882KA1 also disables all its output buffers except for
Yn/Yn, QxODTn, QxCKEn and FBOUT/FBOUT. The Yn/Yn and FBOUT/FBOUT outputs continue to drive a valid
phase accurate clock signal. The QxODTn and QxCKEn outputs are driven Low. The register output buffers are
Hi-Z tQDIS clock after QxCKEn is driven Low. This is shown in the next figure.
Power Down Mode Entry and Exit with IBT Off
(1) i, j only apply for QuadCS capable register. When QuadCS is enabled, i = 2, j = 3.
(2) QuadCS disabled: During CKE Power Down Entry/Exit, driving DCS[1,0] LOW is illegal as it will force
SSTE32882KA0 into Register Control Word access mode.
(3)Upon CKE Power Down exit, QxCSn will be held HIGH for maximum of 1 tCK regardless of what DCSn input
level is. For all other operation QxCSn outputs will follow DCSn inputs.
H or L
CK
RESET
DAn,DBAn
DRAS,
DODTn
DCKEn
DCAS,
DWE
High or Low
Low
High
tInDIS
High or Low
High
Hi-z
High
Yn
QxAn,
QxODTn
High or Low
Low
High
High or Low
High
Hi-z
QxRAS,
QxCAS,
QxWE
QxCKEn
High or Low
Low
Hi-z
tFixedoutput
Hi-z
tQDIS
Output buffers are Hi-z
n
n-1
n+4
n+8
n+12
n+16
n+20
n
n-1
n+4
n+8
n+12
n+16
n+20
QxBAn
High or Low
High
Hi-z
High
Low
High
Hi-z
High or Low
Low
High or Low
PAR_IN
Hi-z
QxCS[i,0]
QxCS[j,1]
DCS[i,0]
DCS[j,1]
H or L
Either or both DCKEn inputs are driven High
Either or both QxCKEn outputs are driven High
tEN
see Note 3
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SSTE32882HLBBKG8 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER
SSTE32882KA1AKG 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882KA1AKG8 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882KA1AKG8/M 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel
SSTE32882TNA1AKG8 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel
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