- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄98142 > SSTE32882HLBBKG (INTEGRATED DEVICE TECHNOLOGY INC) SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176 PDF資料下載
參數(shù)資料
| 型號： | SSTE32882HLBBKG |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘及定時(shí) |
| 英文描述： | SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176 |
| 封裝： | 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176 |
| 文件頁數(shù)： | 35/69頁 |
| 文件大?。?/td> | 1263K |
| 代理商： | SSTE32882HLBBKG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁當(dāng)前第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
40
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Power Down Mode Entry and Exit with IBT On
(1) i, j only apply for QuadCS capable register. When QuadCS is enabled, i = 2, j = 3.
(2) QuadCS disabled: During CKE Power Down Entry/Exit, driving DCS[1,0] LOW is illegal as it will force SSTE32882KA0 into
Register Control Word access mode.
(3) UPon CKE Power Down exit, QxCSn will be held HIGH for a maximum of 1 tCK regardless of what DCSn input level is. For
all other operation, QxCSn outputs will follow DCSn inputs.
To re-enable the SSTE32882KA1 from this Power Down Mode with IBT on, valid logic levels are required at all
device inputs when either or both DCKEn inputs are driven High. Upon either DCKE0 or DCKE1 input going High,
the SSTE32882KA1 immediately starts driving High on the appropriate QxCKEn signals. The QxCSn signals are
driven high and the QxODTn signals follow the inputs. Other output signals QxRAS, QxCAS, QxWE and QxAddr
are driven either high or low to ensure stable valid logic on all device outputs when QxCKEn goes High. The device
drives output signals to these levels for tFIXEDOUTPUT to allow input receivers to be stablized. After the input
receivers are stablized, the register output follow their corresponding input levels. When exiting CKE power down
mode, either one of the Chip Select register inputs DCSn can be asserted for 1 tCK. For QuadCS capable register,
when working in quad rank mode, either two of the Chip Select register inputs DCSn can be asserted for 1 tCK. The
device guarantees that input receivers are stablized within tFIXEDOUTPUT clocks after DCKEn input is driven High.
This is shown in the previous diagram.
CK
RESET
DAn,DBAn
DRAS,
DODTn
DCKEn
DCAS,
DWE
High, Low or Toggling
High or Low
Low
High
tInDIS
High
Hi-z
High
Yn
QxAn,
QxODTn
Follows Input (High, Low or Toggling)
Low
High
Hi-z
QxRAS,
QxCAS,
QxWE
QxCKEn
High or Low
Hi-z
tFixedoutput
Hi-z
tQDIS
Output buffers are Hi-z
n
n-1
n+4
n+8
n+12
n+16
n+20
n
n-1
n+4
n+8
n+12
n+16
n+20
QxBAn
DCS[j,1]
High or Low
High
Hi-z
High
Follows Input (High or Low)
Hi-z
High or Low
H or L
H, L or Hi-Z
H or L
Follows Input (High or Low)
tFixedoutput
High or Low
H, L or Hi-Z
High
H or L
PAR_IN
Hi-z
H, L or Hi-Z
DCS[i,0]
QxCS[j,1]
QxCS[i,0]
H, L or Hi-Z
H or L
Either or both DCKEn inputs are driven High
Either or both QxCKEn outputs are driven High
tEN
see Note 3
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SSTUA32864EC,557 | SSTU SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PBGA96 |
| SSTUA32866EC/G | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| SSTUA32866EC,557 | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| SSTUA32866EC/G,551 | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
| SSTUA32866EC/G,557 | 32866 SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PBGA96 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SSTE32882HLBBKG8 | 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER |
| SSTE32882KA1AKG | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTE32882KA1AKG8 | 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube |
| SSTE32882KA1AKG8/M | 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel |
| SSTE32882TNA1AKG8 | 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。