參數(shù)資料
型號: SSTE32882HLBBKG
廠商: INTEGRATED DEVICE TECHNOLOGY INC
元件分類: 時鐘及定時
英文描述: SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝: 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁數(shù): 50/69頁
文件大小: 1263K
代理商: SSTE32882HLBBKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
54
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
The IBT control is also located in this control word, with two options of 100
Ω or 150Ω which can be selected to
adapt to different system scenarios. At power-up, the SSTE32882KA1 IBT defaults to 100
Ω. The system controller
can reprogram the termination resistance to 150
Ω by setting this bit. Only the DAn, DBAn, DRAS, DCAS, DWE,
DCSn, DODTn, DCKEn, and PAR_IN inputs have the IBT. The CK, CK, FBIN, FBIN, RESET, and MIRROR inputs
do not have IBT.
If MIRROR is ‘HIGH’ then it is assumed the register is located on the back side of a module where two registers are
tied together on the input side. In this case, for the register on the back side, the IBT are turned off on all inputs
except the DCSn and DODTn inputs.
The following diagram illustrates the pre-launch feature whereby double loaded nets in a 2-rank configuration can
be driven with an earlier signal compared to output clock and control in order to compensate for the slower signal
travel speed. This timing applies at all supported frequencies.
Effective IBT Tolerance Requirement
Min
Max
Total Effective IBT Value Tolerance1
1 Example: for 100 Ohm IBT, Min = 90 Ohms, Max = 110 Ohms
-10%
+10%
Mismatch Tolerance Between R-IBT-Up and R-IBT-Down
Max
Mismatch Tolerance Between R-IBT-Up
and R-IBT-Down1
1 (1 - R-IBT-Up/R-IBT-Down) *100% < ABS(5%)
ABS(5%)
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