參數(shù)資料
型號： SSTE32882HLBBKG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時鐘及定時
英文描述： SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝： 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁數(shù)： 20/69頁
文件大?。?/td> 1263K
代理商： SSTE32882HLBBKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
27
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Clock Driver Characteristics at Application Frequency (frequency band 1)
Symbol
Parameter
Conditions
DDR3/
DDR3-800
DDR3/
DDR3L-1066
DDR3/
DDR3L-1333
DDR3/
DDR3L-1600
DDR3-1866
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
tJIT(CC+)
Cycle-to-cycle period
jitter
0
40
0
40040030025
ps
tJIT(CC-)
Cycle-to-cycle period
jitter
-400-400-40
0
-30
0-25
0
ps
tSTAB
Stabilization time
-6-6-6-
6
-5
s
tFDYN
Dynamic phase offset
-50
50
-50
50
-50
50
-40
40
-30
30
ps
tCKSK
Fractional Clock
Output skew1
-15-15
-15-10
-
10
ps
tJIT(PER) Yn Clock Period jitter
-40
40
-40
40
-40
40
-30
30
-25
25
ps
tJIT(HPER) Half period jitter
-50
50
-50
50
-50
50
-40
40
-35
35
ps
tPWH/PWL
Yn pulse width
HIG/LOW duration3
tPW = 1/2tCK -
ItJIT(hper)minI
to 1/2tCK -
ItJIT(hper)maxI
1.200 1.300 0.888 0.988 0.700 0.800 0.585 0.665 0.501 0.571
ns
tQSK12
Qn Output to Yn clock
tolerance (Standard
1/2-Clock
Pre-Launch)
Output
Inversion
enabled
-150
250
-150
250
-150
250
-140
140
-135
125
ps
Output
Inversion
disabled
-150
350
-150
350
-150
350
-140
240
-135
225
tQSK24
Qn Output to Yn clock
tolerance (3/4 Clock
Pre-Launch)
Output
Inversion
enabled
-150
250
-150
250
-150
250
-140
140
-135
125
ps
Output
Inversion
disabled
-150
350
-150
350
-150
350
-140
240
-135
225
tSTAOFF
Average delay
through the register
beween the input
clock and output clock
over “n” cycles5.
(1.5V operation)
Standard
1/2-Clock
Pre-Launch
tSTAOFF = tPDM
+ 1/2 tCK
1.9
2.25
1.59
1.94
1.40
1.75
1.28
1.63
1.19
1.54
ns
3/4 Clock
Pre-Launch
tSTAOFF = tPDM
+ 3/4 tCK
2.53
2.88
2.06
2.41
1.77
2.12
1.59
1.94
1.45
1.80
ns
Average delay
through the register
beween the input
clock and output
clock5.
(1.35V operation)
Standard
1/2-Clock
Pre-Launch
tSTAOFF = tPDM
+ 1/2 tCK
1.90
2.45
1.59
2.14
1.40
1.95
1.28
1.83
-
ns
3/4 Clock
Pre-Launch
tSTAOFF = tPDM
+ 3/4 tCK
2.53
3.08
2.06
2.61
1.77
2.32
1.59
2.14
-
ns
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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SSTE32882TNA1AKG8 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel
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