參數(shù)資料
型號(hào)： SSTE32882HLBBKG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝： 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁(yè)數(shù)： 30/69頁(yè)
文件大小： 1263K
代理商： SSTE32882HLBBKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
36
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
Two Parity-Error Occurrences Separated by two Clock Cycles of no Error Occurrence
1 CK left out for better visibility.
The next figure shows the parity diagram with two parity-error occurrences; during chip-select and chip-deselect
modes. The diagram assumes the occurrence of both parity errors when data is clocked in at the n and n+1 input
clock cycles (PAR_IN clocked in on the n+1 and n+2 input clock cycles). Parity error in the chip-select mod is
detected, but parity error in the chip-deselect mode is ignored.
Parity-Error Occurrence In Chip-Deselect Mode
1 CK left out for better visibility.
The next figure shows the parity diagram with two parity-error occurrences; during normal operation and during
control register programming. The diagram assumes the occurrence of both parity errors when data is clocked in
at the n and n+3 input clock cycles (PAR_IN clocked in on the n+1 and n+4 input clock cycles). The data on the n+3
input clock pulse is intended for the control mode register. Parity error during control mode register programming is
detected and the parity functionality is the same as during normal operation. If a parity error occurs, the command
is ignored.
CK(1)
CA
Input
PAR_IN
CA0
P0
CA1
P1
CA2
P2
ERROUT
n
n+1
n+2
n+3
n+4
n+5
n+6
ERROUT resulting from CA0 - P0, followed by 2nd error in CA3 - P3
n+7
n+8
n+9
CA3
P3
P4
CA4
CA5
P5
CK(1)
CA
Input
PAR_IN
CA0
P0
CA1
P1
CA2
P2
ERROUT
nn+1
n+2n+3
n+4n+5
n+6
ERROUT resulting from CA0 - P0, subsequent parity errors during DCSx high ignored
DCSx
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SSTE32882TNA1AKG8 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel
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