參數(shù)資料
型號(hào)： SSTE32882HLBBKG
廠商： INTEGRATED DEVICE TECHNOLOGY INC
元件分類： 時(shí)鐘及定時(shí)
英文描述： SSTE SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PBGA176
封裝： 8 X 13.50 MM, 0.65 MM PITCH, GREEN, MO-246F, CABGA-176
文件頁(yè)數(shù)： 33/69頁(yè)
文件大?。?/td> 1263K
代理商： SSTE32882HLBBKG
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
39
SSTE32882KA1
7314/5
CONFIDENTIAL - THE INFORMATION IN THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE
SSTE32882KA1
1.25V/1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT
COMMERCIAL TEMPERATURE RANGE
To re-enable the register from this power saving state, valid logic levels are required at all register inputs when
either or both DCKEn inputs are driven high. Upon either DCKE0 or DCKE1 input going High, the register
immediately starts driving High on the appropriate QxCKEn signal. The QxCSn signals are driven High and
QxODTn signals are driven Low. Other output signals QxRAS, QxCAS, QxWE, and QxAddr are driven either high
or low to ensure stable valid logic an all register outputs when QxCKEn goes High. The register drives output
signals to these levels for tFIXEDOUTPUT to allow input receivers to be stabilized. After the input recievers are
stabilized, the register output follow their corresponding input levels. When exiting CKE power down mode, either
one of the Chip Select register inputs DCSn can be asserted for 1 tCK. For QuadCS capable register, when working
in quad rank mode, either two of the Chip Select register inputs DCSn can be asserted for 1 tCK. The register
guarantees that input receivers are stabilized within tFIXEDOUTPUT clocks after DCKEn input is driven High. This is
shown in the previous diagram.
REGISTER CKE POWER DOWN WITH IBT ON
Upon entry into CKE Power Down Mode with IBT on, all register input buffers excluding IBT are disabled except for
CK/CK, DCKEn, DODTn, FBIN/FBIN, and RESET. The SSTE32882KA1 disables input buffers within tInDIS clocks
after latching both DCKEn Low. In order to eliminate any false parity check error, the PAR_IN input buffer has to be
kept active for 1 tCK after the Address and Command input buffers are disabled. After tInDIS, the register can
tolerate floating input except for CK/CK, DCKEn, DODTn and RESET. The SSTE32882KA1 also disables all its
output buffers except for Yn/Yn, QxODTn, QxCKEn and FBOUT/FBOUT. The Yn/Yn and FBOUT/FBOUT outputs
continue to drive a valid phase accurate clock signal. The QxCKEn outputs are driven Low. The register output
buffers are Hi-Z tQDIS clock after QxCKEn is driven Low. This is shown below.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SSTE32882HLBBKG8 制造商:Integrated Device Technology Inc 功能描述:Registering Clock Driver 176-Pin CABGA T/R 制造商:Integrated Device Technology Inc 功能描述:176 BGA (GREEN) - Tape and Reel 制造商:Integrated Device Technology Inc 功能描述:DDR3 LV REGISTER
SSTE32882KA1AKG 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882KA1AKG8 功能描述:寄存器 RoHS:否 制造商:NXP Semiconductors 邏輯類型:CMOS 邏輯系列:HC 電路數(shù)量:1 最大時(shí)鐘頻率:36 MHz 傳播延遲時(shí)間: 高電平輸出電流:- 7.8 mA 低電平輸出電流:7.8 mA 電源電壓-最大:6 V 最大工作溫度:+ 125 C 封裝 / 箱體:SOT-38 封裝:Tube
SSTE32882KA1AKG8/M 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel
SSTE32882TNA1AKG8 制造商:Integrated Device Technology Inc 功能描述:DDR3 REGISTER - Tape and Reel
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