參數(shù)資料
型號： SPAKD56366PV120
廠商： MOTOROLA INC
元件分類： 數(shù)字信號處理
英文描述： 24-BIT, 120 MHz, OTHER DSP, PQFP144
封裝： TQFP-144
文件頁數(shù)： 97/147頁
文件大小： 2156K
代理商： SPAKD56366PV120
Specifications
External Memory Expansion Port (Port A)
MOTOROLA
DSP56366 Advance Information
2-23
Notes:
1.
The number of wait states for Page mode access is specified in the DCR.
2.
The refresh period is specified in the DCR.
3.
The asynchronous delays specified in the expressions are valid for DSP56366.
4.
All the timings are calculated for the worst case. Some of the timings are better for specific cases (e.g., tPC equals
3
× TC for read-after-read or write-after-write sequences).
5.
BRW[1:0] (DRAM Control Register bits) defines the number of wait states that should be inserted in each DRAM
out-of-page access.
6.
RD deassertion will always occur after CAS deassertion; therefore, the restricted timing is tOFF and not tGZ.
7.
There are no DRAMs fast enough to fit to two wait states Page mode @ 100MHz (See Figure 2-11)
Table 2-11 DRAM Page Mode Timings, Three Wait States1, 2, 3
No.
Characteristics
Symbol
Expression
Min
Max
Unit
131
Page mode cycle time for two consecutive accesses of the same
direction
tPC
2
× TC
40.0
—
ns
Page mode cycle time for mixed (read and write) accesses
1.25
× TC
35.0
—
132 CAS assertion to data valid (read)
tCAC
2
× TC 7.0
—
13.0
ns
133 Column address valid to data valid (read)
tAA
3
× TC 7.0
—
23.0
ns
134 CAS deassertion to data not valid (read hold time)
tOFF
0.0
—
ns
135 Last CAS assertion to RAS deassertion
tRSH
2.5
× TC 4.0
21.0
—
ns
136 Previous CAS deassertion to RAS deassertion
tRHCP
4.5
× TC 4.0
41.0
—
ns
137 CAS assertion pulse width
tCAS
2
× TC 4.0
16.0
—
ns
138
Last CAS deassertion to RAS assertion5
BRW[1:0] = 00
tCRP
2.25
× TC 6.0
—
ns
BRW[1:0] = 01
3.75
× TC 6.0
—
ns
BRW[1:0] = 10
4.75
× TC 6.0
41.5
—
ns
BRW[1:0] = 11
6.75
× TC 6.0
61.5
—
ns
139 CAS deassertion pulse width
tCP
1.5
× TC 4.0
11.0
—
ns
140 Column address valid to CAS assertion
tASC
TC 4.0
6.0
—
ns
141 CAS assertion to column address not valid
tCAH
2.5
× TC 4.0
21.0
—
ns
142 Last column address valid to RAS deassertion
tRAL
4
× TC 4.0
36.0
—
ns
143 WR deassertion to CAS assertion
tRCS
1.25
× TC 4.0
8.5
—
ns
144 CAS deassertion to WR assertion
tRCH
0.75
× TC 4.0
3.5
—
ns
145 CAS assertion to WR deassertion
tWCH
2.25
× TC 4.2
18.3
—
ns
146 WR assertion pulse width
tWP
3.5
× TC 4.5
30.5
—
ns
147 Last WR assertion to RAS deassertion
tRWL
3.75
× TC 4.3
33.2
—
ns
148 WR assertion to CAS deassertion
tCWL
3.25
× TC 4.3
28.2
—
ns
149 Data valid to CAS assertion (write)
tDS
0.5
× TC 4.0
1.0
—
ns
Table 2-10 DRAM Page Mode Timings, Two Wait States1, 2, 3, 7 (Continued)
No.
Characteristics
Symbol
Expression
66 MHz
80 MHz
Unit
Min
Max
Min
Max
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