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參數(shù)資料
| 型號(hào)： | SPAKD56366PV120 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | 24-BIT, 120 MHz, OTHER DSP, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁(yè)數(shù)： | 13/147頁(yè) |
| 文件大?。?/td> | 2156K |
| 代理商： | SPAKD56366PV120 |
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Signal/Connection Descriptions
External Memory Expansion Port (Port A)
MOTOROLA
DSP56366 Advance Information
1-7
CAS
Outpu
t
Tri-stated
Column Address Strobe— When the DSP is the bus master, CAS is an active-low
output used by DRAM to strobe the column address. Otherwise, if the bus mastership
enable (BME) bit in the DRAM control register is cleared, the signal is tri-stated.
RD
Outpu
t
Tri-stated
Read Enable—When the DSP is the bus master, RD is an active-low output that is
asserted to read external memory on the data bus (D0-D23). Otherwise, RD is tri-
stated.
WR
Outpu
t
Tri-stated
Write Enable—When the DSP is the bus master, WR is an active-low output that is
asserted to write external memory on the data bus (D0-D23). Otherwise, WR is tri-
stated.
TA
Input
Ignored
Input
Transfer Acknowledge—If the DSP is the bus master and there is no external bus
activity, or the DSP is not the bus master, the TA input is ignored. The TA input is a
data transfer acknowledge (DTACK) function that can extend an external bus cycle
indefinitely. Any number of wait states (1, 2. . .infinity) may be added to the wait
states inserted by the BCR by keeping TA deasserted. In typical operation, TA is
deasserted at the start of a bus cycle, is asserted to enable completion of the bus cycle,
and is deasserted before the next bus cycle. The current bus cycle completes one clock
period after TA is asserted synchronous to the internal system clock. The number of
wait states is determined by the TA input or by the bus control register (BCR),
whichever is longer. The BCR can be used to set the minimum number of wait states
in external bus cycles.
In order to use the TA functionality, the BCR must be programmed to at least one wait
state. A zero wait state access cannot be extended by TA deassertion, otherwise
improper operation may result. TA can operate synchronously or asynchronously,
depending on the setting of the TAS bit in the operating mode register (OMR).
TA functionality may not be used while performing DRAM type accesses, otherwise
improper operation may result.
BR
Outpu
t
Output
(deasserted
)
Bus Request—BR is an active-low output, never tri-stated. BR is asserted when the
DSP requests bus mastership. BR is deasserted when the DSP no longer needs the bus.
BR may be asserted or deasserted independent of whether the DSP56366 is a bus
master or a bus slave. Bus “parking” allows BR to be deasserted even though the
DSP56366 is the bus master. (See the description of bus “parking” in the BB signal
description.) The bus request hold (BRH) bit in the BCR allows BR to be asserted
under software control even though the DSP does not need the bus. BR is typically
sent to an external bus arbitrator that controls the priority, parking, and tenure of each
master on the same external bus. BR is only affected by DSP requests for the external
bus, never for the internal bus. During hardware reset, BR is deasserted and the
arbitration is reset to the bus slave state.
Table 1-7 External Bus Control Signals (Continued)
Signal
Name
Type
State
during
Reset
Signal Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SPB3 | RECTANGULAR CONNECTOR |
| SPB4 | RECTANGULAR CONNECTOR |
| SPB5 | RECTANGULAR CONNECTOR |
| SPBH5 | RECTANGULAR CONNECTOR |
| SPD16A1002AL13 | Thin Film Resistor Network Isolated and Bussed Circuits RoHS compliant available |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SPAKDSP303AG100 | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC SPAKDSP303AG100 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| SPAKDSP303GC100 | 制造商:Motorola Inc 功能描述: |
| SPAKDSP303VF100 | 功能描述:IC DSP 24BIT 100MHZ 196-MAPBGA RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:DSP563xx 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類(lèi)型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類(lèi)型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤(pán) 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
| SPAKDSP303VL100 | 功能描述:IC DSP 24BIT 100MHZ 196-MAPBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:DSP563xx 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類(lèi)型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類(lèi)型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤(pán) |
| SPAKDSP311VF150 | 功能描述:IC DSP 24BIT 196-MAPBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:DSP56K/Symphony 標(biāo)準(zhǔn)包裝:40 系列:TMS320DM64x, DaVinci™ 類(lèi)型:定點(diǎn) 接口:I²C，McASP，McBSP 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:160kB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:0°C ~ 90°C 安裝類(lèi)型:表面貼裝 封裝/外殼:548-BBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:548-FCBGA（27x27） 包裝:托盤(pán) 配用:TMDSDMK642-0E-ND - DEVELPER KIT W/NTSC CAMERA296-23038-ND - DSP STARTER KIT FOR TMS320C6416296-23059-ND - FLASHBURN PORTING KIT296-23058-ND - EVAL MODULE FOR DM642TMDSDMK642-ND - DEVELOPER KIT W/NTSC CAMERA |
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