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參數(shù)資料
| 型號(hào)： | SPAKD56366PV120 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | 24-BIT, 120 MHz, OTHER DSP, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數(shù)： | 11/147頁 |
| 文件大小： | 2156K |
| 代理商： | SPAKD56366PV120 |
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4-2
DSP56366 Advance Information
MOTOROLA
Design Considerations
Electrical Design Considerations
To define a value approximately equal to a junction-to-board thermal resistance, the thermal
resistance is measured from the junction to where the leads are attached to the case.
If the temperature of the package case (TT) is determined by a thermocouple, the thermal
resistance is computed using the value obtained by the equation
(TJ – TT)/PD.
As noted above, the junction-to-case thermal resistances quoted in this data sheet are determined using the
first definition. From a practical standpoint, that value is also suitable for determining the junction
temperature from a case thermocouple reading in forced convection environments. In natural convection,
using the junction-to-case thermal resistance to estimate junction temperature from a thermocouple reading
on the case of the package will estimate a junction temperature slightly hotter than actual temperature.
Hence, the new thermal metric, thermal characterization parameter or
ΨJT, has been defined to be (TJ –
TT)/PD. This value gives a better estimate of the junction temperature in natural convection when using the
surface temperature of the package. Remember that surface temperature readings of packages are subject
to significant errors caused by inadequate attachment of the sensor to the surface and to errors caused by
heat loss to the sensor. The recommended technique is to attach a 40-gauge thermocouple wire and bead to
the top center of the package with thermally conductive epoxy.
ELECTRICAL DESIGN CONSIDERATIONS
Use the following list of recommendations to assure correct DSP operation:
Provide a low-impedance path from the board power supply to each VCC pin on the DSP and from
the board ground to each GND pin.
Use at least six 0.01–0.1
F bypass capacitors positioned as close as possible to the four sides of
the package to connect the VCC power source to GND.
Ensure that capacitor leads and associated printed circuit traces that connect to the chip VCC and
GND pins are less than 1.2 cm (0.5 inch) per capacitor lead.
Use at least a four-layer PCB with two inner layers for VCC and GND.
CAUTION
This device contains circuitry protecting against
damage due to high static voltage or electrical
fields. However, normal precautions should be
taken to avoid exceeding maximum voltage ratings.
Reliability of operation is enhanced if unused
inputs are tied to an appropriate logic voltage level
(e.g., either GND or VCC). The suggested value for
a pullup or pulldown resistor is 10 kOhm.
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