參數(shù)資料
型號： SPAKD56366PV120
廠商： MOTOROLA INC
元件分類： 數(shù)字信號處理
英文描述： 24-BIT, 120 MHz, OTHER DSP, PQFP144
封裝： TQFP-144
文件頁數(shù)： 24/147頁
文件大小： 2156K
代理商： SPAKD56366PV120
1-8
DSP56366 Advance Information
MOTOROLA
Signal/Connection Descriptions
Interrupt and Mode Control
INTERRUPT AND MODE CONTROL
The interrupt and mode control signals select the chip’s operating mode as it comes out of hardware reset.
After RESET is deasserted, these inputs are hardware interrupt request lines.
BG
Input
Ignored
Input
Bus Grant—BG is an active-low input. BG is asserted by an external bus arbitration
circuit when the DSP56366 becomes the next bus master. When BG is asserted, the
DSP56366 must wait until BB is deasserted before taking bus mastership. When BG is
deasserted, bus mastership is typically given up at the end of the current bus cycle.
This may occur in the middle of an instruction that requires more than one external bus
cycle for execution.
For proper BG operation, the asynchronous bus arbitration enable bit (ABE) in the
OMR register must be set.
BB
Input/
Outpu
t
Input
Bus Busy—BB is a bidirectional active-low input/output. BB indicates that the bus is
active. Only after BB is deasserted can the pending bus master become the bus master
(and then assert the signal again). The bus master may keep BB asserted after ceasing
bus activity regardless of whether BR is asserted or deasserted. This is called “bus
parking” and allows the current bus master to reuse the bus without rearbitration until
another device requires the bus. The deassertion of BB is done by an “active pull-up”
method (i.e., BB is driven high and then released and held high by an external pull-up
resistor).
For proper BB operation, the asynchronous bus arbitration enable bit (ABE) in the
OMR register must be set.
BB requires an external pull-up resistor.
Table 1-7 External Bus Control Signals (Continued)
Signal
Name
Type
State
during
Reset
Signal Description
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