參數(shù)資料
型號: SPAKD56366PV120
廠商: MOTOROLA INC
元件分類: 數(shù)字信號處理
英文描述: 24-BIT, 120 MHz, OTHER DSP, PQFP144
封裝: TQFP-144
文件頁數(shù): 133/147頁
文件大小: 2156K
代理商: SPAKD56366PV120
2-56
DSP56366 Advance Information
MOTOROLA
Specifications
Serial Host Interface (SHI) I2C Protocol Timing
Programming the Serial Clock
The programmed serial clock cycle, TI2CCP, is specified by the value of the HDM[7:0] and HRS bits of the
HCKR (SHI clock control register).
The expression for TI2CCP is
TI2CCP = [TC × 2 × (HDM[7:0] + 1) × (7 × (1 – HRS) + 1)]
where
HRS is the prescaler rate select bit. When HRS is cleared, the fixed
divide-by-eight prescaler is operational. When HRS is set, the prescaler is bypassed.
HDM[7:0] are the divider modulus select bits. A divide ratio from 1 to 256 (HDM[7:0] = $00
to $FF) may be selected.
In I2C mode, the user may select a value for the programmed serial clock cycle from
6
× TC
(if HDM[7:0] = $02 and HRS = 1)
to
4096
× TC
(if HDM[7:0] = $FF and HRS = 0)
188
HREQ in assertion to first SCL edge
TAS;RQI
0.5
× TI2CCP -
0.5
× TC - 21
ns
Filters bypassed
4440
1041
Narrow filters enabled
4373
999
Wide filters enabled
4373
958
189
First SCL edge to HREQ in not
asserted (HREQ in hold time)
tHO;RQI
0.0
0.0
ns
Notes:
1.
VCC = 3.16 V ± 0.16 V; TJ = –40°C to +105°C
2.
Pull-up resistor: RP (min) = 1.5 kOhm
3.
Capacitive load: Cb (max) = 400 pF
4.
It is recommended to enable the wide filters when operating in the I2C Standard Mode.
5.
It is recommended to enable the narrow filters when operating in the I2C Fast Mode.
Table 2-20 SHI I2C Protocol Timing (Continued)
No.
Characteristics1,2,3
Symbol/
Expression
Standard Mode4
Fast Mode5
Unit
Min
Max
Min
Max
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