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參數(shù)資料
| 型號(hào)： | SM320F28335GHHAEP |
| 廠商： | Texas Instruments |
| 文件頁(yè)數(shù)： | 83/167頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DIGITAL SIGNAL CTLR 179-BGA |
| 產(chǎn)品培訓(xùn)模塊： | ControlSUITE Motor Signal Chain Overview TPS75005 Single IC Power for C2000 MCU |
| 標(biāo)準(zhǔn)包裝： | 189 |
| 系列： | TMS320F28x3x Delfino™, C2000™ |
| 核心處理器： | C28x |
| 芯體尺寸： | 32-位 |
| 速度： | 150MHz |
| 連通性： | CAN，EBI/EMI，I²C，McBSP，SCI，SPI，UART/USART |
| 外圍設(shè)備： | DMA，POR，PWM，WDT |
| 輸入/輸出數(shù)： | 88 |
| 程序存儲(chǔ)器容量： | 512KB（256K x 16） |
| 程序存儲(chǔ)器類型： | 閃存 |
| RAM 容量： | 34K x 16 |
| 電壓 - 電源 (Vcc/Vdd)： | 1.805 V ~ 1.995 V |
| 數(shù)據(jù)轉(zhuǎn)換器： | A/D 16x12b |
| 振蕩器型： | 內(nèi)部 |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 179-LFBGA |
| 包裝： | 托盤(pán) |
| 產(chǎn)品目錄頁(yè)面： | 718 (CN2011-ZH PDF) |
| 其它名稱： | 296-25243 |
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SPRS581D – JUNE 2009 – REVISED MAY 2012
2.2
Signal Descriptions
Table 2-2 describes the signals. The GPIO function (shown in Italics) is the default at reset. The peripheral
signals that are listed under them are alternate functions. Some peripheral functions may not be available
in all devices. See Table 2-1 for details. Inputs are not 5-V tolerant. All pins capable of producing an
XINTF output function have a drive strength of 8 mA (typical). This is true even if the pin is not configured
for XINTF functionality. All other pins have a drive strength of 4-mA drive typical (unless otherwise
indicated). All GPIO pins are I/O/Z and have an internal pullup, which can be selectively enabled/disabled
on a per-pin basis. This feature only applies to the GPIO pins. The pullups on GPIO0-GPIO11 pins are not
enabled at reset. The pullups on GPIO12-GPIO34 are enabled upon reset.
Table 2-2. Signal Descriptions
PIN NO.
PGF/P
NAME
DESCRIPTION (1)
GHH
GJZ
TP
BALL #
PIN #
JTAG
JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system
control of the operations of the device. If this signal is not connected or driven low, the
device operates in its functional mode, and the test reset signals are ignored.
NOTE: TRST is an active high test pin and must be maintained low at all times during
TRST
78
M10
L11
normal device operation. An external pulldown resistor is recommended on this pin. The
value of this resistor should be based on drive strength of the debugger pods applicable to
the design. A 2.2-k
resistor generally offers adequate protection. Since this is application-
specific, it is recommended that each target board be validated for proper operation of the
debugger and the application. (I,
↓)
TCK
87
N12
M14
JTAG test clock with internal pullup (I,
↑)
JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into
TMS
79
P10
M12
the TAP controller on the rising edge of TCK. (I,
↑)
JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register
TDI
76
M9
N12
(instruction or data) on a rising edge of TCK. (I,
↑)
JTAG scan out, test data output (TDO). The contents of the selected register (instruction or
TDO
77
K9
N13
data) are shifted out of TDO on the falling edge of TCK. (O/Z 8 mA drive)
Emulator pin 0. When TRST is driven high, this pin is used as an interrupt to or from the
emulator system and is defined as input/output through the JTAG scan. This pin is also
used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state
and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the
device into boundary-scan mode. (I/O/Z, 8 mA drive
↑)
EMU0
85
L11
N7
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor
should be based on the drive strength of the debugger pods applicable to the design. A
2.2-k
to 4.7-k resistor is generally adequate. Since this is application-specific, it is
recommended that each target board be validated for proper operation of the debugger
and the application.
Emulator pin 1. When TRST is driven high, this pin is used as an interrupt to or from the
emulator system and is defined as input/output through the JTAG scan. This pin is also
used to put the device into boundary-scan mode. With the EMU0 pin at a logic-high state
and the EMU1 pin at a logic-low state, a rising edge on the TRST pin would latch the
device into boundary-scan mode. (I/O/Z, 8 mA drive
↑)
EMU1
86
P12
P8
NOTE: An external pullup resistor is recommended on this pin. The value of this resistor
should be based on the drive strength of the debugger pods applicable to the design. A
2.2-k
to 4.7-k resistor is generally adequate. Since this is application-specific, it is
recommended that each target board be validated for proper operation of the debugger
and the application.
FLASH
VDD3VFL
84
M11
L9
3.3-V Flash Core Power Pin. This pin should be connected to 3.3 V at all times.
TEST1
81
K10
M7
Test Pin. Reserved for TI. Must be left unconnected. (I/O)
TEST2
82
P11
L7
Test Pin. Reserved for TI. Must be left unconnected. (I/O)
(1)
I = Input, O = Output, Z = High impedance, OD = Open drain,
↑ = Pullup, ↓ = Pulldown
22
Introduction
Copyright 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): SM320F28335-EP
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