
SPRS581D – JUNE 2009 – REVISED MAY 2012
6-6
Clock Timing
.....................................................................................................................
1106-7
Power-on Reset
.................................................................................................................
1116-8
Warm Reset
.....................................................................................................................
1126-9
Example of Effect of Writing Into PLLCR Register
.........................................................................
1136-10
General-Purpose Output Timing
..............................................................................................
1146-11
Sampling Mode
.................................................................................................................
1146-12
General-Purpose Input Timing
................................................................................................
1156-13
IDLE Entry and Exit Timing
....................................................................................................
1166-14
STANDBY Entry and Exit Timing Diagram
..................................................................................
1176-15
HALT Wake-Up Using GPIOn
.................................................................................................
1196-16
PWM Hi-Z Characteristics
.....................................................................................................
1206-17
ADCSOCAO or ADCSOCBO Timing
........................................................................................
1226-18
External Interrupt Timing
.......................................................................................................
1226-19
SPI Master Mode External Timing (Clock Phase = 0)
.....................................................................
1256-20
SPI Master Mode External Timing (Clock Phase = 1)
.....................................................................
1276-21
SPI Slave Mode External Timing (Clock Phase = 0)
.......................................................................
1296-22
SPI Slave Mode External Timing (Clock Phase = 1)
.......................................................................
1306-23
Relationship Between XTIMCLK and SYSCLKOUT
.......................................................................
1336-24
Example Read Access
.........................................................................................................
1356-25
Example Write Access
.........................................................................................................
1366-26
Example Read With Synchronous XREADY Access
......................................................................
1386-27
Example Read With Asynchronous XREADY Access
.....................................................................
1396-28
Write With Synchronous XREADY Access
..................................................................................
1416-29
Write With Asynchronous XREADY Access
................................................................................
1426-30
External Interface Hold Waveform
............................................................................................
1446-31
XHOLD/XHOLDA Timing Requirements (XCLKOUT = 1/2 XTIMCLK)
..................................................
1456-32
ADC Power-Up Control Bit Timing
...........................................................................................
1476-33
ADC Analog Input Impedance Model
........................................................................................
1486-34
Sequential Sampling Mode (Single-Channel) Timing
......................................................................
1496-35
Simultaneous Sampling Mode Timing
.......................................................................................
1506-36
McBSP Receive Timing
........................................................................................................
1546-37
McBSP Transmit Timing
.......................................................................................................
1546-38
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
...................................................
1556-39
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 0
...................................................
1566-40
McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 1
...................................................
1566-41
McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
...................................................
1576
List of Figures
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