參數(shù)資料
型號: SM320F28335GHHAEP
廠商: Texas Instruments
文件頁數(shù): 115/167頁
文件大?。?/td> 0K
描述: IC DIGITAL SIGNAL CTLR 179-BGA
產(chǎn)品培訓(xùn)模塊: ControlSUITE
Motor Signal Chain Overview
TPS75005 Single IC Power for C2000 MCU
標(biāo)準(zhǔn)包裝: 189
系列: TMS320F28x3x Delfino™, C2000™
核心處理器: C28x
芯體尺寸: 32-位
速度: 150MHz
連通性: CAN,EBI/EMI,I²C,McBSP,SCI,SPI,UART/USART
外圍設(shè)備: DMA,POR,PWM,WDT
輸入/輸出數(shù): 88
程序存儲器容量: 512KB(256K x 16)
程序存儲器類型: 閃存
RAM 容量: 34K x 16
電壓 - 電源 (Vcc/Vdd): 1.805 V ~ 1.995 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 179-LFBGA
包裝: 托盤
產(chǎn)品目錄頁面: 718 (CN2011-ZH PDF)
其它名稱: 296-25243
X1
XCLKIN
(3.3-Vclockinput
fromexternal
oscillator)
On-chip
oscillator
X2
PLLSTS[OSCOFF]
OSCCLK
PLL
VCOCLK
4-bitMultiplierPLLCR[DIV]
OSCCLKor
VCOCLK
CLKIN
OSCCLK
0
PLLSTS[PLLOFF]
n
n 0
PLLSTS[DIVSEL]
/1
/2
/4
External
Crystalor
Resonator
To
CPU
SPRS581D – JUNE 2009 – REVISED MAY 2012
Table 3-13. PLL, Clocking, Watchdog, and Low-Power Mode Registers
Name
Address
Size (x16)
Description
PLLSTS
0x00 7011
1
PLL Status Register
Reserved
0x00 7012 - 0x00 7018
7
Reserved
HISPCP
0x00 701A
1
High-Speed Peripheral Clock Pre-Scaler Register
LOSPCP
0x00 701B
1
Low-Speed Peripheral Clock Pre-Scaler Register
PCLKCR0
0x00 701C
1
Peripheral Clock Control Register 0
PCLKCR1
0x00 701D
1
Peripheral Clock Control Register 1
LPMCR0
0x00 701E
1
Low Power Mode Control Register 0
Reserved
0x00 701F
1
Low Power Mode Control Register 1
PCLKCR3
0x00 7020
1
Peripheral Clock Control Register 3
PLLCR
0x00 7021
1
PLL Control Register
SCSR
0x00 7022
1
System Control and Status Register
WDCNTR
0x00 7023
1
Watchdog Counter Register
Reserved
0x00 7024
1
Reserved
WDKEY
0x00 7025
1
Watchdog Reset Key Register
Reserved
0x00 7026 - 0x00 7028
3
Reserved
WDCR
0x00 7029
1
Watchdog Control Register
Reserved
0x00 702A - 0x00 702D
6
Reserved
MAPCNF
0x00 702E
1
ePWM/HRPWM Re-map Register
3.6.1
OSC and PLL Block
Figure 3-7 shows the OSC and PLL block.
Figure 3-7. OSC and PLL Block Diagram
The on-chip oscillator circuit enables a crystal/resonator to be attached to the F28335 using the X1 and X2
pins. If the on-chip oscillator is not used, an external oscillator can be used in either one of the following
configurations:
1. A 3.3-V external oscillator can be directly connected to the XCLKIN pin. The X2 pin should be left
unconnected and the X1 pin tied low. The logic-high level in this case should not exceed VDDIO.
2. A 1.9-V (1.8-V for 100 MHz devices) external oscillator can be directly connected to the X1 pin. The X2
pin should be left unconnected and the XCLKIN pin tied low. The logic-high level in this case should
not exceed VDD.
The three possible input-clock configurations are shown in Figure 3-8 through Figure 3-10.
Copyright 2009–2012, Texas Instruments Incorporated
Functional Overview
51
Product Folder Link(s): SM320F28335-EP
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