參數(shù)資料
型號(hào): SM320F28335GHHAEP
廠商: Texas Instruments
文件頁(yè)數(shù): 6/167頁(yè)
文件大小: 0K
描述: IC DIGITAL SIGNAL CTLR 179-BGA
產(chǎn)品培訓(xùn)模塊: ControlSUITE
Motor Signal Chain Overview
TPS75005 Single IC Power for C2000 MCU
標(biāo)準(zhǔn)包裝: 189
系列: TMS320F28x3x Delfino™, C2000™
核心處理器: C28x
芯體尺寸: 32-位
速度: 150MHz
連通性: CAN,EBI/EMI,I²C,McBSP,SCI,SPI,UART/USART
外圍設(shè)備: DMA,POR,PWM,WDT
輸入/輸出數(shù): 88
程序存儲(chǔ)器容量: 512KB(256K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 34K x 16
電壓 - 電源 (Vcc/Vdd): 1.805 V ~ 1.995 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 179-LFBGA
包裝: 托盤
產(chǎn)品目錄頁(yè)面: 718 (CN2011-ZH PDF)
其它名稱: 296-25243
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SPRS581D – JUNE 2009 – REVISED MAY 2012
6.4.1
Reducing Current Consumption
The F28335 DSC incorporates a method to reduce the device current consumption. Since each peripheral
unit has an individual clock-enable bit, reduction in current consumption can be achieved by turning off the
clock to any peripheral module that is not used in a given application. Furthermore, any one of the three
low-power modes could be taken advantage of to reduce the current consumption even further. Table 6-2
indicates the typical reduction in current consumption achieved by turning off the clocks.
Table 6-2. Typical Current Consumption by Various
Peripherals (at 150 MHz)(1)
PERIPHERAL
IDD CURRENT
MODULE
REDUCTION/MODULE (mA)(2)
ADC
8(3)
I2C
2.5
eQEP
5
ePWM
5
eCAP
2
SCI
5
SPI
4
eCAN
8
McBSP
7
CPU - Timer
2
XINTF
10(4)
DMA
10
FPU
15
(1)
All peripheral clocks are disabled upon reset. Writing to/reading from
peripheral registers is possible only after the peripheral clocks are
turned on.
(2)
For peripherals with multiple instances, the current quoted is per
module. For example, the 5 mA number quoted for ePWM is for one
ePWM module.
(3)
This number represents the current drawn by the digital portion of
the ADC module. Turning off the clock to the ADC module results in
the elimination of the current drawn by the analog portion of the ADC
(IDDA18) as well.
(4)
Operating the XINTF bus has a significant effect on IDDIO current. It
will increase considerably based on the following:
How many address/data pins toggle from one cycle to another
How fast they toggle
Whether 16-bit or 32-bit interface is used and
The load on these pins.
Following are other methods to reduce power consumption further:
The Flash module may be powered down if code is run off SARAM. This results in a current reduction
of 35 mA (typical) in the VDD3VFL rail.
IDDIO current consumption is reduced by 15 mA (typical) when XCLKOUT is turned off.
Significant savings in IDDIO may be realized by disabling the pullups on pins that assume an output
function and on XINTF pins. A savings of 35 mW (typical) can be achieved by this.
The baseline IDD current (current when the core is executing a dummy loop with no peripherals enabled) is
165 mA, (typical). To arrive at the IDD current for a given application, the current-drawn by the peripherals
(enabled by that application) must be added to the baseline IDD current.
Copyright 2009–2012, Texas Instruments Incorporated
Electrical Specifications
103
Product Folder Link(s): SM320F28335-EP
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