參數(shù)資料
型號: SM320F28335GHHAEP
廠商: Texas Instruments
文件頁數(shù): 151/167頁
文件大?。?/td> 0K
描述: IC DIGITAL SIGNAL CTLR 179-BGA
產(chǎn)品培訓(xùn)模塊: ControlSUITE
Motor Signal Chain Overview
TPS75005 Single IC Power for C2000 MCU
標(biāo)準(zhǔn)包裝: 189
系列: TMS320F28x3x Delfino™, C2000™
核心處理器: C28x
芯體尺寸: 32-位
速度: 150MHz
連通性: CAN,EBI/EMI,I²C,McBSP,SCI,SPI,UART/USART
外圍設(shè)備: DMA,POR,PWM,WDT
輸入/輸出數(shù): 88
程序存儲器容量: 512KB(256K x 16)
程序存儲器類型: 閃存
RAM 容量: 34K x 16
電壓 - 電源 (Vcc/Vdd): 1.805 V ~ 1.995 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 16x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 85°C
封裝/外殼: 179-LFBGA
包裝: 托盤
產(chǎn)品目錄頁面: 718 (CN2011-ZH PDF)
其它名稱: 296-25243
SPRS581D – JUNE 2009 – REVISED MAY 2012
The SCI port operation is configured and controlled by the registers listed in Table 4-10, Table 4-11, and
Table 4-10. SCI-A Registers(1)
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
SCICCRA
0x7050
1
SCI-A Communications Control Register
SCICTL1A
0x7051
1
SCI-A Control Register 1
SCIHBAUDA
0x7052
1
SCI-A Baud Register, High Bits
SCILBAUDA
0x7053
1
SCI-A Baud Register, Low Bits
SCICTL2A
0x7054
1
SCI-A Control Register 2
SCIRXSTA
0x7055
1
SCI-A Receive Status Register
SCIRXEMUA
0x7056
1
SCI-A Receive Emulation Data Buffer Register
SCIRXBUFA
0x7057
1
SCI-A Receive Data Buffer Register
SCITXBUFA
0x7059
1
SCI-A Transmit Data Buffer Register
SCIFFTXA(2)
0x705A
1
SCI-A FIFO Transmit Register
SCIFFRXA(2)
0x705B
1
SCI-A FIFO Receive Register
SCIFFCTA(2)
0x705C
1
SCI-A FIFO Control Register
SCIPRIA
0x705F
1
SCI-A Priority Control Register
(1)
Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2)
These registers are new registers for the FIFO mode.
Table 4-11. SCI-B Registers(1) (2)
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
SCICCRB
0x7750
1
SCI-B Communications Control Register
SCICTL1B
0x7751
1
SCI-B Control Register 1
SCIHBAUDB
0x7752
1
SCI-B Baud Register, High Bits
SCILBAUDB
0x7753
1
SCI-B Baud Register, Low Bits
SCICTL2B
0x7754
1
SCI-B Control Register 2
SCIRXSTB
0x7755
1
SCI-B Receive Status Register
SCIRXEMUB
0x7756
1
SCI-B Receive Emulation Data Buffer Register
SCIRXBUFB
0x7757
1
SCI-B Receive Data Buffer Register
SCITXBUFB
0x7759
1
SCI-B Transmit Data Buffer Register
SCIFFTXB(2)
0x775A
1
SCI-B FIFO Transmit Register
SCIFFRXB(2)
0x775B
1
SCI-B FIFO Receive Register
SCIFFCTB(2)
0x775C
1
SCI-B FIFO Control Register
SCIPRIB
0x775F
1
SCI-B Priority Control Register
(1)
Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2)
These registers are new registers for the FIFO mode.
Table 4-12. SCI-C Registers(1) (2)
NAME
ADDRESS
SIZE (x16)
DESCRIPTION
SCICCRC
0x7770
1
SCI-C Communications Control Register
SCICTL1C
0x7771
1
SCI-C Control Register 1
SCIHBAUDC
0x7772
1
SCI-C Baud Register, High Bits
SCILBAUDC
0x7773
1
SCI-C Baud Register, Low Bits
SCICTL2C
0x7774
1
SCI-C Control Register 2
(1)
Registers in this table are mapped to Peripheral Frame 2 space. This space only allows 16-bit accesses. 32-bit accesses produce
undefined results.
(2)
These registers are new registers for the FIFO mode.
84
Peripherals
Copyright 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): SM320F28335-EP
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