參數(shù)資料
型號(hào)： SM320F28335GHHAEP
廠商： Texas Instruments
文件頁數(shù)： 113/167頁
文件大小： 0K
描述： IC DIGITAL SIGNAL CTLR 179-BGA
產(chǎn)品培訓(xùn)模塊： ControlSUITE
Motor Signal Chain Overview
TPS75005 Single IC Power for C2000 MCU
標(biāo)準(zhǔn)包裝： 189
系列： TMS320F28x3x Delfino™, C2000™
核心處理器： C28x
芯體尺寸： 32-位
速度： 150MHz
連通性： CAN，EBI/EMI，I²C，McBSP，SCI，SPI，UART/USART
外圍設(shè)備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 88
程序存儲(chǔ)器容量： 512KB（256K x 16）
程序存儲(chǔ)器類型： 閃存
RAM 容量： 34K x 16
電壓 - 電源 (Vcc/Vdd)： 1.805 V ~ 1.995 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 179-LFBGA
包裝： 托盤
產(chǎn)品目錄頁面： 718 (CN2011-ZH PDF)
其它名稱： 296-25243
SPRS581D – JUNE 2009 – REVISED MAY 2012
List of Figures
2-1
176-Pin PGF/PTP LQFP (Top View)
.......................................................................................... 14
2-2
179-Ball GHH MicroStar BGA (Upper Left Quadrant) (Bottom View)
.................................................. 15
2-3
179-Ball GHH MicroStar BGA (Upper Right Quadrant) (Bottom View)
................................................. 16
2-4
179-Ball GHH MicroStar BGA (Lower Left Quadrant) (Bottom View)
.................................................. 17
2-5
179-Ball GHH MicroStar BGA (Lower Right Quadrant) (Bottom View)
................................................. 18
2-6
176-Ball GJZ Plastic BGA (Upper Left Quadrant) (Bottom View)
.......................................................... 19
2-7
176-Ball GJZ Plastic BGA (Upper Right Quadrant) (Bottom View)
........................................................ 20
2-8
176-Ball GJZ Plastic BGA (Lower Left Quadrant) (Bottom View)
.......................................................... 21
2-9
176-Ball GJZ Plastic BGA (Lower Right Quadrant) (Bottom View)
........................................................ 21
3-1
Functional Block Diagram
...................................................................................................... 31
3-2
Memory Map
...................................................................................................................... 33
3-3
External and PIE Interrupt Sources
............................................................................................ 46
3-4
External Interrupts
................................................................................................................ 46
3-5
Multiplexing of Interrupts Using the PIE Block
............................................................................... 47
3-6
Clock and Reset Domains
...................................................................................................... 50
3-7
OSC and PLL Block Diagram
................................................................................................... 51
3-8
Using a 3.3-V External Oscillator
............................................................................................... 52
3-9
Using a 1.9-V External Oscillator
............................................................................................... 52
3-10
Using the Internal Oscillator
.................................................................................................... 52
3-11
Watchdog Module
................................................................................................................ 54
4-1
DMA Functional Block Diagram
................................................................................................ 57
4-2
CPU-Timers
....................................................................................................................... 58
4-3
CPU-Timer Interrupt Signals and Output Signal
............................................................................. 58
4-4
Multiple PWM Modules
.......................................................................................................... 60
4-5
ePWM Submodules Showing Critical Internal Signal Interconnections
................................................... 63
4-6
eCAP Functional Block Diagram
............................................................................................... 67
4-7
eQEP Functional Block Diagram
............................................................................................... 68
4-8
Block Diagram of the ADC Module
............................................................................................ 71
4-9
ADC Pin Connections With Internal Reference
.............................................................................. 72
4-10
ADC Pin Connections With External Reference
............................................................................. 73
4-11
McBSP Module
.................................................................................................................. 76
4-12
eCAN Block Diagram and Interface Circuit
................................................................................... 79
4-13
eCAN-A Memory Map
........................................................................................................... 80
4-14
eCAN-B Memory Map
........................................................................................................... 81
4-15
Serial Communications Interface (SCI) Module Block Diagram
............................................................ 85
4-16
SPI Module Block Diagram (Slave Mode)
.................................................................................... 88
4-17
I2C Peripheral Module Interfaces
.............................................................................................. 89
4-18
GPIO MUX Block Diagram
...................................................................................................... 91
4-19
Qualification Using Sampling Window
......................................................................................... 96
4-20
External Interface Block Diagram
.............................................................................................. 97
4-21
Typical 16-bit Data Bus XINTF Connections
................................................................................. 98
4-22
Typical 32-bit Data Bus XINTF Connections
................................................................................. 98
6-1
SM320F28335 Operating Life Derating Chart
.............................................................................. 100
6-2
Typical Operational Current Versus Frequency
............................................................................ 105
6-3
Typical Operational Power Versus Frequency
............................................................................. 105
6-4
Emulator Connection Without Signal Buffering for the DSP
.............................................................. 106
6-5
3.3-V Test Load Circuit
......................................................................................................... 107
Copyright 2009–2012, Texas Instruments Incorporated
List of Figures
5
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