Table 3-14. PLLCR(1) " />
參數(shù)資料
型號： SM320F28335GHHAEP
廠商： Texas Instruments
文件頁數(shù)： 117/167頁
文件大?。?/td> 0K
描述： IC DIGITAL SIGNAL CTLR 179-BGA
產(chǎn)品培訓(xùn)模塊： ControlSUITE
Motor Signal Chain Overview
TPS75005 Single IC Power for C2000 MCU
標準包裝： 189
系列： TMS320F28x3x Delfino™, C2000™
核心處理器： C28x
芯體尺寸： 32-位
速度： 150MHz
連通性： CAN，EBI/EMI，I²C，McBSP，SCI，SPI，UART/USART
外圍設(shè)備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 88
程序存儲器容量： 512KB（256K x 16）
程序存儲器類型： 閃存
RAM 容量： 34K x 16
電壓 - 電源 (Vcc/Vdd)： 1.805 V ~ 1.995 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 179-LFBGA
包裝： 托盤
產(chǎn)品目錄頁面： 718 (CN2011-ZH PDF)
其它名稱： 296-25243
SPRS581D – JUNE 2009 – REVISED MAY 2012
Table 3-14. PLLCR(1) Bit Descriptions
SYSCLKOUT (CLKIN)
PLLCR[DIV] VALUE(2) (3)
PLLSTS[DIVSEL] = 0 or 1
PLLSTS[DIVSEL] = 2
PLLSTS[DIVSEL] = 3
0000 (PLL bypass)
OSCCLK/4 (Default)
OSCCLK/2
OSCCLK
0001
(OSCCLK * 1)/4
(OSCCLK * 1)/2
–
0010
(OSCCLK * 2)/4
(OSCCLK * 2)/2
–
0011
(OSCCLK * 3)/4
(OSCCLK * 3)/2
–
0100
(OSCCLK * 4)/4
(OSCCLK * 4)/2
–
0101
(OSCCLK * 5)/4
(OSCCLK * 5)/2
–
0110
(OSCCLK * 6)/4
(OSCCLK * 6)/2
–
0111
(OSCCLK * 7)/4
(OSCCLK * 7)/2
–
1000
(OSCCLK * 8)/4
(OSCCLK * 8)/2
–
1001
(OSCCLK * 9)/4
(OSCCLK * 9)/2
–
1010
(OSCCLK * 10)/4
(OSCCLK * 10)/2
–
1011 - 1111
Reserved
(1)
By default, PLLSTS[DIVSEL] is configured for /4. (The boot ROM changes this to /2.) PLLSTS[DIVSEL] must be 0 before writing to the
PLLCR and should be changed only after PLLSTS[PLLLOCKS] = 1.
(2)
The PLL control register (PLLCR) and PLL Status Register (PLLSTS) are reset to their default state by the XRS signal or a watchdog
reset only. A reset issued by the debugger or the missing clock detect logic have no effect.
(3)
This register is EALLOW protected.
Table 3-15. CLKIN Divide Options
PLLSTS [DIVSEL]
CLKIN DIVIDE
0
/4
1
/4
2
/2
3
/1(1)
(1)
This mode can be used only when the PLL is bypassed or off.
The PLL-based clock module provides two modes of operation:
Crystal-operation - This mode allows the use of an external crystal/resonator to provide the time base
to the device.
External clock source operation - This mode allows the internal oscillator to be bypassed. The device
clocks are generated from an external clock source input on the X1 or the XCLKIN pin.
Table 3-16. Possible PLL Configuration Modes
CLKIN AND
PLL MODE
REMARKS
PLLSTS[DIVSEL]
SYSCLKOUT
Invoked by the user setting the PLLOFF bit in the PLLSTS register. The PLL block
is disabled in this mode. This can be useful to reduce system noise and for low
0, 1
OSCCLK/4
PLL Off
power operation. The PLLCR register must first be set to 0x0000 (PLL Bypass)
2
OSCCLK/2
before entering this mode. The CPU clock (CLKIN) is derived directly from the
3
OSCCLK/1
input clock on either X1/X2, X1 or XCLKIN.
PLL Bypass is the default PLL configuration upon power-up or after an external
0, 1
OSCCLK/4
reset (XRS). This mode is selected when the PLLCR register is set to 0x0000 or
PLL Bypass
2
OSCCLK/2
while the PLL locks to a new frequency after the PLLCR register has been
3
OSCCLK/1
modified. In this mode, the PLL itself is bypassed but the PLL is not turned off.
Achieved by writing a non-zero value n into the PLLCR register. Upon writing to the
0, 1
OSCCLK*n/4
PLL Enable
PLLCR the device will switch to PLL Bypass mode until the PLL locks.
2
OSCCLK*n/2
Copyright 2009–2012, Texas Instruments Incorporated
Functional Overview
53
Product Folder Link(s): SM320F28335-EP
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