參數(shù)資料
型號： SM320F28335GHHAEP
廠商： Texas Instruments
文件頁數(shù)： 5/167頁
文件大?。?/td> 0K
描述： IC DIGITAL SIGNAL CTLR 179-BGA
產(chǎn)品培訓(xùn)模塊： ControlSUITE
Motor Signal Chain Overview
TPS75005 Single IC Power for C2000 MCU
標(biāo)準(zhǔn)包裝： 189
系列： TMS320F28x3x Delfino™, C2000™
核心處理器： C28x
芯體尺寸： 32-位
速度： 150MHz
連通性： CAN，EBI/EMI，I²C，McBSP，SCI，SPI，UART/USART
外圍設(shè)備： DMA，POR，PWM，WDT
輸入/輸出數(shù)： 88
程序存儲器容量： 512KB（256K x 16）
程序存儲器類型： 閃存
RAM 容量： 34K x 16
電壓 - 電源 (Vcc/Vdd)： 1.805 V ~ 1.995 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 85°C
封裝/外殼： 179-LFBGA
包裝： 托盤
產(chǎn)品目錄頁面： 718 (CN2011-ZH PDF)
其它名稱： 296-25243
SPRS581D – JUNE 2009 – REVISED MAY 2012
6.4
Current Consumption
Table 6-1. Current Consumption by Power-Supply Pins at 150-MHz SYSCLKOUT
IDD
IDDIO
(1)
IDD3VFL
(2)
IDDA18
(3)
IDDA33
(4)
MODE
TEST CONDITIONS
TYP(5)
MAX
TYP(5)
MAX
TYP
MAX
TYP(5)
MAX
TYP(5)
MAX
The following peripheral
clocks are enabled:
ePWM1/2/3/4/5/6
eCAP1/2/3/4/5/6
eQEP1/2
eCAN-A
SCI-A/B (FIFO
Operational
mode)
290 mA
315 mA
30 mA
50 mA
35 mA
40 mA
30 mA
35 mA
1.5 mA
2 mA
(Flash)(6)
SPI-A (FIFO mode)
ADC
I2C
CPU Timer 0/1/2
All PWM pins are toggled
at 150 kHz.
All I/O pins are left
unconnected.(7)
Flash is powered down.
XCLKOUT is turned off.
The following peripheral
clocks are enabled:
IDLE
100 mA
120 mA
60
μA
120
μA
2
μA
10
μA
5
μA
60
μA
15
μA
20
μA
eCAN-A
SCI-A
SPI-A
I2C
Flash is powered down.
STANDBY
8 mA
15 mA
60
μA
120
μA
2
μA
10
μA
5
μA
60
μA
15
μA
20
μA
Peripheral clocks are off.
Flash is powered down.
HALT(8)
Peripheral clocks are off.
150
μA
60
μA
120
μA
2
μA
10
μA
5
μA
60
μA
15
μA
20
μA
Input clock is disabled.(9)
(1)
IDDIO current is dependent on the electrical loading on the I/O pins.
(2)
The IDD3VFL current indicated in this table is the flash read-current and does not include additional current for erase/write operations.
During flash programming, extra current is drawn from the VDD and VDD3VFL rails, as indicated in Table 6-66. If the user application
involves on-board flash programming, this extra current must be taken into account while architecting the power-supply stage.
(3)
IDDA18 includes current into VDD1A18 and VDD2A18 pins. In order to realize the IDDA18 currents shown for IDLE, STANDBY, and HALT,
clock to the ADC module must be turned off explicitly by writing to the PCLKCR0 register.
(4)
IDDA33 includes current into VDDA2 and VDDAIO pins.
(5)
The TYP numbers are applicable over room temperature and nominal voltage. MAX numbers are at 125°C, and MAX voltage (VDD = 2.0
V; VDDIO, VDD3VFL, VDDA = 3.6 V).
(6)
When the identical code is run off SARAM, IDD would increase as the code operates with zero wait states.
(7)
The following is done in a loop:
Data is continuously transmitted out of the SCI-A, SCI-B, SPI-A, McBSP-A, and eCAN-A ports.
Multiplication/addition operations are performed.
Watchdog is reset.
ADC is performing continuous conversion. Data from ADC is transferred to SARAM through the DMA.
32-bit read/write of the XINTF is performed.
GPIO19 is toggled.
(8)
HALT mode IDD currents will increase with temperature in a non-linear fashion.
(9)
If a quartz crystal or ceramic resonator is used as the clock source, the HALT mode shuts down the internal oscillator.
NOTE
The peripheral - I/O multiplexing implemented in the device prevents all available peripherals
from being used at the same time. This is because more than one peripheral function may
share an I/O pin. It is, however, possible to turn on the clocks to all the peripherals at the
same time, although such a configuration is not useful. If this is done, the current drawn by
the device will be more than the numbers specified in the current consumption tables.
102
Electrical Specifications
Copyright 2009–2012, Texas Instruments Incorporated
Product Folder Link(s): SM320F28335-EP
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