參數(shù)資料
型號(hào): SC28L92A1B-S
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQFP44
封裝: 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁(yè)數(shù): 73/73頁(yè)
文件大?。?/td> 336K
代理商: SC28L92A1B-S
SC28L92_7
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 — 19 December 2007
9 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
5.2 Pin description
Table 2.
Pin description for 80xxx bus interface (Intel)
Symbol
Pin
Type
Description
PLCC44 QFP44
HVQFN48
I/M
12
11
7
I
Bus conguration: When HIGH or not connected congures the bus
interface to the conditions shown in this table.
D0
28
22
23
I/O
Data bus: Bidirectional 3-state data bus used to transfer commands,
data and status between the DUART and the CPU. D0 is the least
signicant bit.
D1
18
12
14
I/O
D2
27
21
22
I/O
D3
19
13
15
I/O
D4
26
20
21
I/O
D5
20
14
16
I/O
D6
25
19
20
I/O
D7
21
15
17
I/O
CEN
39
33
35
I
Chip enable: Active LOW input signal. When LOW, data transfers
between the CPU and the DUART are enabled on D0 to D7 as
controlled by the WRN, RDN and A0 to A3 inputs. When HIGH, places
the D0 to D7 lines in the 3-state condition.
WRN
9
3
I
Write strobe: When LOW and CEN is also LOW, the contents of the
data bus is loaded into the addressed register. The transfer occurs on
the rising edge of the signal.
RDN
10
4
I
Read strobe: When LOW and CEN is also LOW, causes the contents
of the addressed register to be presented on the data bus. The read
cycle begins on the falling edge of RDN.
A0
2
40
44
I
Address inputs: Select the DUART internal registers and ports for
read/write operations.
A1
4
42
46
I
A2
6
44
48
I
A3
7
1
I
RESET
38
32
34
I
Reset: A HIGH level clears internal registers (SRA, SRB, IMR, ISR,
OPR and OPCR), puts OP0 to OP7 in the HIGH state, stops the
counter/timer, and puts channels A and B in the inactive state, with the
TxDA and TxDB outputs in the mark (HIGH) state. Sets MR pointer to
MR1. See Figure 10.
INTRN
24
18
19
O
Interrupt request: Active LOW, open-drain, output which signals the
CPU that one or more of the eight maskable interrupting conditions are
true. This pin requires a pull-up device.
X1/CLK
36
30
32
I
Crystal 1: Crystal or external clock input. A crystal or clock of the
specied limits must be supplied at all times. When a crystal is used, a
capacitor must be connected from this pin to ground (see Figure 17).
X2
37
31
33
O
Crystal 2: Connection for other side of the crystal. When a crystal is
used, a capacitor must be connected from this pin to ground (see
Figure 17). If X1/CLK is driven from an external source, this pin must
be left open.
RxDA
35
29
31
I
Channel A receiver serial data input: The least signicant bit is
received rst. See note on drive levels at block diagram (Figure 1).
RxDB
11
5
I
Channel B receiver serial data input: The least signicant bit is
received rst. See note on drive levels at block diagram (Figure 1).
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SC28L92A1BS,528 功能描述:UART 接口集成電路 3V-5V 1CH UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC28L92A1BS,551 功能描述:UART 接口集成電路 3V-5V 1CH UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC28L92A1BS,557 功能描述:UART 接口集成電路 3V-5V 1CH UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC28L92A1BS-F 功能描述:UART 接口集成電路 3V-5V 1CH UART INTEL/MOT INTRF RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC28L92A1BS-S 功能描述:UART 接口集成電路 3V-5V 1CH UART INTEL/MOT INTRF RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel