參數(shù)資料
型號: SC28L92A1B-S
廠商: NXP SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQFP44
封裝: 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁數(shù): 29/73頁
文件大小: 336K
代理商: SC28L92A1B-S
SC28L92_7
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 — 19 December 2007
35 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
7.3.3 Command registers
7.3.3.1
Command Register channel A (CRA)
CRA is a register used to supply commands to channel A. Multiple commands can be
specied in a single write to CRA as long as the commands are non-conicting, e.g., the
enable transmitter and reset transmitter commands cannot be specied in a single
command word.
Table 38.
CRA - Command register channel A (address 0x2) and
CRB - Command register channel B (address 0xA) bit allocation
7
6
5
4
3
2
1
0
channel command code
disable Tx
enable Tx
disable Rx
enable Rx
Table 39.
CRA - Command register channel A (address 0x2) bit description
Bit
Symbol
Description
7 to 4
-
Miscellaneous commands. Execution of the commands in the upper four bits
of this register must be separated by 3 X1 clock edges. Other reads or writes
(including writes to the lower four bits) may be inserted to achieve this
separation. A description of miscellaneous commands is given in Table 40.
3
-
Disable channel A transmitter. This command terminates transmitter operation
and reset the TxDRY and TxEMT status bits. However, if a character is being
transmitted or if a character is in the Tx FIFO when the transmitter is disabled,
the transmission of the character(s) is completed before assuming the inactive
state.
2
-
Enable channel A transmitter. Enables operation of the channel A transmitter.
The TxRDY and TxEMT status bits will be asserted if the transmitter is idle.
1
-
Disable channel A receiver. This command terminates operation of the
receiver immediately-a character being received will be lost. The command
has no effect on the receiver status bits or any other control registers. If the
special multi-drop mode is programmed, the receiver operates even if it is
disabled. See Section 6.3.10.
0
-
Enable channel A receiver. Enables operation of the channel A receiver. If not
in the special wake-up mode, this also forces the receiver into the search for
start-bit state.
Table 40.
Miscellaneous commands
Command
Description
0000
No command.
0001
Reset MR pointer. Causes the channel A MR pointer to point to MR1.
0010
Reset receiver. Resets the channel A receiver as if a hardware reset had been
applied. The receiver is disabled and the FIFO is ushed.
0011
Reset transmitter. Resets the channel A transmitter as if a hardware reset had
been applied.
0100
Reset error status. Clears the channel A received break, parity error, and overrun
error bits in the status register (SRA[7:4]). Used in character mode to clear OE
status (although RB, PE and FE bits will also be cleared) and in block mode to clear
all error status after a block of data has been received.
0101
Reset channel A break change interrupt. Causes the channel A break detect
change bit in the interrupt status register (ISR[2]) to be cleared to zero.
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SC28L92A1BS,557 功能描述:UART 接口集成電路 3V-5V 1CH UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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