參數(shù)資料
型號： SC28L92A1B-S
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQFP44
封裝： 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁數(shù)： 33/73頁
文件大?。?/td> 336K
代理商： SC28L92A1B-S
SC28L92_7
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 — 19 December 2007
39 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
7.3.4.2
Status Register channel B (SRB)
[1]
These status bits are appended to the corresponding data character in the receive FIFO. A read of the
status provides these bits [7:5] from the top of the FIFO together with bits [4:0]. These bits are cleared by a
reset error status command. In character mode they are discarded when the corresponding data character
is read from the FIFO. In block error mode, the error-reset command (command 0x4 or receiver reset) must
used to clear block error conditions.
The bit denitions for this register are identical to the bit denitions for SRA, except that all
status applies to the channel B receiver and transmitter and the corresponding inputs and
outputs.
7.3.5 Output Conguration Control Register (OPCR)
This register controls the signal presented by the OP[7:2] pins. The signal presented by
the OP[1:0] pins is controlled by the Rx, Tx, and the command register. The default
condition of the OP pins is to drive the complement of the data in the OPR[7:0] register.
When OP[7:2] pins drive DMA or interrupt type signals, they switch to open-drain
conguration. Otherwise, they drive strong logic 0 or logic 1 levels.
Table 43.
SRB - Status register channel B (address 0x9) bit allocation
7
6
5
4
3
2
1
0
received
framing
parity
error[1]
overrun
error
TxEMTB
TxRDYB
RxFULLB
RxRDYB
Table 44.
OPCR - Output conguration control register (address 0xD) bit allocation
7
6
5
4
3
2
1
0
congure
OP7
congure
OP6
congure
OP5
congure
OP4
congure OP3
congure OP2
Table 45.
OPCR - Output conguration control register (address 0xD) bit description
Bit
Symbol
Description
7
-
OP7 output select
0 = The complement of OPR[7]
1 = The channel B transmitter interrupt output which is the complement of
ISR[4]. When in this mode OP7 acts as an open-drain output. Note that
this output is not masked by the contents of the IMR.
6
-
OP6 output select
0 = The complement of OPR[6]
1 = The channel A transmitter interrupt output which is the complement of
ISR[0]. When in this mode OP6 acts as an open-drain output. Note that
this output is not masked by the contents of the IMR.
5
-
OP5 output select
0 = The complement of OPR[5]
1 = The channel B receiver interrupt output which is the complement of
ISR[5]. When in this mode OP5 acts as an open-drain output. Note that
this output is not masked by the contents of the IMR.
4
-
OP4 output select
0 = The complement of OPR[4]
1 = The channel A receiver interrupt output which is the complement of
ISR[1]. When in this mode OP4 acts as an open-drain output. Note that
this output is not masked by the contents of the IMR.
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參數(shù)描述
SC28L92A1BS,528 功能描述:UART 接口集成電路 3V-5V 1CH UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC28L92A1BS,551 功能描述:UART 接口集成電路 3V-5V 1CH UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC28L92A1BS,557 功能描述:UART 接口集成電路 3V-5V 1CH UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC28L92A1BS-F 功能描述:UART 接口集成電路 3V-5V 1CH UART INTEL/MOT INTRF RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC28L92A1BS-S 功能描述:UART 接口集成電路 3V-5V 1CH UART INTEL/MOT INTRF RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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