參數(shù)資料
型號(hào)： SC28L92A1B-S
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQFP44
封裝： 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁(yè)數(shù)： 31/73頁(yè)
文件大小： 336K
代理商： SC28L92A1B-S
SC28L92_7
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 — 19 December 2007
37 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
7.3.4 Status registers
7.3.4.1
Status Register channel A (SRA)
[1]
These status bits are appended to the corresponding data character in the receive FIFO. A read of the
status provides these bits [7:5] from the top of the FIFO together with bits [4:0]. These bits are cleared by a
reset error status command. In character mode they are discarded when the corresponding data character
is read from the FIFO. In block error mode, the error-reset command (command 0x4 or receiver reset) must
used to clear block error conditions.
Table 41.
SRA - Status register channel A (address 0x1) bit allocation
7
6
5
4
3
2
1
0
received
break[1]
framing
error[1]
parity
overrun
error
TxEMTA
TxRDYA
RxFULLA
RxRDYA
Table 42.
SRA - Status register channel A (address 0x1) bit description
Bit
Symbol
Description
7
-
Channel A received break.
0 = no
1 = yes
This bit indicates that an all zero character of the programmed length has been
received without a stop bit. Only a single FIFO position is occupied when a
break is received: further entries to the FIFO are inhibited until the RxDA line
returns to the marking state for at least one-half a bit time two successive
edges of the internal or external 1
× clock. This will usually require a HIGH
time of one X1 clock period or 3 X1 edges since the clock of the controller
is not synchronous to the X1 clock.
When this bit is set, the channel A change in break bit in the ISR (ISR[2]) is set.
ISR[2] is also set when the end of the break condition, as dened above, is
detected.
The break detect circuitry can detect breaks that originate in the middle of a
received character. However, if a break begins in the middle of a character, it
must persist until at least the end of the next character time in order for it to be
detected.
This bit is reset by command 0x4 (0100) written to the command register or by
receiver reset.
6
-
Channel A framing error.
0 = no
1 = yes
This bit, when set, indicates that a stop bit was not detected (not a logic 1)
when the corresponding data character in the FIFO was received. The stop bit
check is made in the middle of the rst stop bit position.
5
-
Channel A parity error.
0 = no
1 = yes
This bit is set when the with parity or force parity mode is programmed and the
corresponding character in the FIFO was received with incorrect parity.
In the special multi-drop mode the parity error bit stores the receive A/D
(Address/Data) bit.
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參數(shù)描述
SC28L92A1BS,528 功能描述:UART 接口集成電路 3V-5V 1CH UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC28L92A1BS,551 功能描述:UART 接口集成電路 3V-5V 1CH UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC28L92A1BS,557 功能描述:UART 接口集成電路 3V-5V 1CH UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC28L92A1BS-F 功能描述:UART 接口集成電路 3V-5V 1CH UART INTEL/MOT INTRF RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC28L92A1BS-S 功能描述:UART 接口集成電路 3V-5V 1CH UART INTEL/MOT INTRF RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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