參數(shù)資料
型號(hào)： SC28L92A1B-S
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, SERIAL COMM CONTROLLER, PQFP44
封裝： 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁數(shù)： 6/73頁
文件大?。?/td> 336K
代理商： SC28L92A1B-S
SC28L92_7
NXP B.V. 2007. All rights reserved.
Product data sheet
Rev. 07 — 19 December 2007
14 of 73
NXP Semiconductors
SC28L92
3.3 V/5.0 V Dual Universal Asynchronous Receiver/Transmitter
receivers, and counter/timer. When OP3 to OP7 are programmed as interrupts, their
output buffers are changed to the open-drain active LOW conguration. The OP pins may
be used for DMA and modem control as well (see Section 7.4).
6.1.4 FIFO conguration
Each receiver and transmitter has a 16 byte FIFO. These FIFOs may be congured to
operate at a ll capacity of either 8 bytes or 16 bytes. This feature may be used if it is
desired to operate the SC28L92 in strict compliance with the SC26C92. The 8 byte or
16 byte mode is controlled by the MR0A[3] bit. A logic 0 value for this bit sets the 8-bit
mode (the default); a logic 1 sets the 16 byte mode. MR0A bit 3 sets the FIFO size for both
channels.
The FIFO ll interrupt level automatically follow the programming of the MR0A[3] bit. See
6.1.5 68xxx mode
When the I/M pin is connected to GND (ground), the operation of the SC28L92 switches to
the bus interface compatible with the Motorola bus interfaces. Several of the pins change
their function as follows:
IP6 becomes IACKN input
RDN becomes DACKN
WRN becomes R/WN
The interrupt vector is enabled and the interrupt vector will be placed on the data bus
when IACKN is asserted LOW. The interrupt vector register is located at address 0xC. The
contents of this register are set to 0x0F on the application of RESETN.
The generation of DACKN uses two positive edges of the X1 clock as the DACKN delay
from the falling edge of CEN. If the CEN is withdrawn before two edges of the X1 clock
occur, the generation of DACKN is terminated. Systems not strictly requiring DACKN
may use the 68xxx mode with the bus timing of the 80xxx mode greatly decreasing the
bus cycle time.
6.2 Timing circuits
6.2.1 Crystal clock
The timing block consists of a crystal oscillator, a baud rate generator, a programmable
16-bit counter/timer, and four clock selectors. The crystal oscillator operates directly from
a crystal connected across the X1/CLK and X2 inputs. If an external clock of the
appropriate frequency is available, it may be connected to X1/CLK. The clock serves as
the basic timing reference for the Baud Rate Generator (BRG), the counter/timer, and
other internal circuits. A clock signal within the limits specied in Section 10 “Dynamic
characteristics” must always be supplied to the DUART. If an external clock is used
instead of a crystal, X1 should be driven using a conguration similar to the one in
Figure 17. Nominal crystal rate is 3.6864 MHz. Rates up to 8 MHz may be used.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
SC28L92A1BS,528 功能描述:UART 接口集成電路 3V-5V 1CH UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC28L92A1BS,551 功能描述:UART 接口集成電路 3V-5V 1CH UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC28L92A1BS,557 功能描述:UART 接口集成電路 3V-5V 1CH UART RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC28L92A1BS-F 功能描述:UART 接口集成電路 3V-5V 1CH UART INTEL/MOT INTRF RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
SC28L92A1BS-S 功能描述:UART 接口集成電路 3V-5V 1CH UART INTEL/MOT INTRF RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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