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參數(shù)資料
| 型號(hào)： | SAA7392HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Channel encoder/decoder CDR60 |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁(yè)數(shù)： | 60/76頁(yè) |
| 文件大?。?/td> | 246K |
| 代理商： | SAA7392HL |
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2000 Mar 21
60
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
Table 137
Selection of integrator bandwidth
Table 138
Selection of loop bandwidth
Table 139
Description of WobbleConfig1 bits, bit 7 = 1
PLLIntBW.2
PLLIntBW.1
PLLIntBW.0
INTEGRATOR BANDWIDTH
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
1.32 kHz for 4.26 MHz system clock
662 Hz for 4.26 MHz system clock
331 Hz for 4.26 MHz system clock
166 Hz for 4.26 MHz system clock
83 Hz for 4.26 MHz system clock
42 Hz for 4.26 MHz system clock
21 Hz for 4.26 MHz system clock
10 Hz for 4.26 MHz system clock
LOOPBW.2
LOOPBW.1
LOOPBW.0
LOOP BANDWIDTH
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
10.6 kHz for 4.26 MHz system clock
5.3 kHz for 4.26 MHz system clock
2.65 kHz for 4.26 MHz system clock
1.32 kHz for 4.26 MHz system clock
662 Hz for 4.26 MHz system clock
331 Hz for 4.26 MHz system clock
166 Hz for 4.26 MHz system clock
83 Hz for 4.26 MHz system clock
BIT
SYMBOL
DESCRIPTION
6
5
4
3
2
1
0
ATIPhold
WinWidth.4
WinWidth.3
WinWidth.2
WinWidth.1
WinWidth.0
When ATIPhold = 1, then Wobble PLL in Hold mode.
This bit is reserved.
Determines the half of the width of the window where ATIP syncs are being accepted for
resynchronization. The unit of WindowWidth is ATIP clock pulses. As an ATIP frame
consists of 42 ATIP clock pulses, the maximum value of WindowWidth that can be
programmed is 21. The reset value is logic 0. The OutOfWindow state can be detected
by reading the ATIPStatus register.
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