參數(shù)資料
型號： SAA7392HL
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： Channel encoder/decoder CDR60
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80
文件頁數(shù)： 26/76頁
文件大小： 246K
代理商： SAA7392HL
2000 Mar 21
26
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
7.5.7
PLL L
OCK
A
ID
2 P
RESET
R
EGISTER
(PLLFM
EAS
)
The PLL setting point for the EFM counting locking strategy is controlled by setting the PLL frequency such that, there
are, on average, a fixed number of EFM transitions per PLL clock period:
PLL Locking Frequency/EFM Transition Frequency = (EFM_Count + 32)/16 = 4.75 in a typical application.
This value (4.75) is dependent on disc and mechanical variations, improvements may be achieved by adjusting the value
slightly.
Table 42
PLL Lock Aid2 Preset Register (address 04H) - WRITE
Table 43
Description of PLLFMeas bits
7.5.8
M
OTOR
C
ONTROL
R
EGISTER
2 (M
OTOR
2)
This is a dual-function register. When read Motor2 gives an indication of the EYE opening of the equalised HF.
Table 44
Eye Open Register (address 0DH) - READ
7
6
5
4
3
2
1
0
RL3_En
EFMns.5
EFMns.4
EFMns.3
EFMns.2
EFMns.1
EFMns.0
BIT
SYMBOL
DESCRIPTION
7
RL3_En
If RL3_En = 0, then EFM transition counting outer PLL lock strategy. If RL3_En = 1,
then RL3 detection PLL outer lock strategy.
This bit is reserved.
These 6 bits select the EFM nominal setting. The default nominal setting should be set
to ‘101110’.
6
5 to 0
EFMns<5:0>
7
6
5
4
3
2
1
0
EOV.7
EOV.6
EOV.5
EOV.4
EOV.3
EOV.2
EOV.1
EOV.0
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