參數(shù)資料
型號： SAA7392HL
廠商： NXP SEMICONDUCTORS
元件分類： 消費家電
英文描述： Channel encoder/decoder CDR60
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80
文件頁數(shù)： 31/76頁
文件大?。?/td> 246K
代理商： SAA7392HL
2000 Mar 21
31
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
7.7.1
C
LOCK
P
RESET
R
EGISTER
(C
LOCK
P
RE
)
This is a dual-function register. When read the status of the Q-channel is returned.
Table 55
Clock Preset Register (address 12H) - READ
Table 56
Description of ClockPre bits
7.7.2
D
ECODER
M
ODE
S
ELECT
R
EGISTER
(D
ECO
M
ODE
)
This is a dual-function register. When read this register holds the Q-channel subcode data.
Table 57
Decoder Mode Select Register (address 13H) - READ
7.7.3
S
UBCODE
R
EAD
E
ND
R
EGISTER
(S
UB
R
EAD
E
ND
)
After finishing a subcode read, the microprocessor must release the interface to allow the SAA7392 to capture new
subcode frames. This is done by issuing a read to SubReadEnd. No data can be read from this register; only the side
effect is important.
Table 58
Subcode Read End Register (address 14H) - READ
7
6
5
4
3
2
1
0
Ready
Busy
CRC OK
BIT
SYMBOL
DESCRIPTION
7
6
Ready
Busy
If Ready = 0, then buffer filling. If Ready = 1, then valid Q subcode frame available.
If Busy = 0, then buffer filling. If Busy = 1, then buffer held (set after reading this register
with Ready = 1).
If CRC OK = 0, then CRC not checked or not OK. If CRC OK = 1, then CRC of
Q-channel checks OK, only valid if Ready = 1.
These 5 bits are reserved.
5
CRC OK
4 to 0
7
6
5
4
3
2
1
0
SubD.7
SubD.6
SubD.5
SubD.4
SubD.3
SubD.2
SubD.1
SubD.0
7
6
5
4
3
2
1
0
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