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參數(shù)資料
| 型號(hào)： | SAA7392HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Channel encoder/decoder CDR60 |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁(yè)數(shù)： | 58/76頁(yè) |
| 文件大?。?/td> | 246K |
| 代理商： | SAA7392HL |
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2000 Mar 21
58
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
7.16.4
EFM C
LOCK
C
ONFIGURATION
R
EGISTER
4
(EFMC
LOCK
C
ON
F4)
This is a dual-function register, the specific function is
controlled by the state of bit 7.
The sample rate of the integrator may be programmed by
writing to this register when the MSB is set to a logic 1.
Higher sample rates let the integrator work faster. This is
effectively the same as increasing the K
i
value.
Good stability and critical damping of the integrator can be
expected with a sample rate of
1
/
98
EFM frames and
K
i
=
2
-7
at n
=
2.
Thepositionerrorset-pointmaybeprogrammedbywriting
to this register when the MSB is set to a logic 0. A position
error setpoint between
64 and 63 can be programmed
using the remaining 7 bits.
On reset this register has the value
8.
Table 132
EFM Clock Configuration Register 4 (address 37H) - WRITE
Table 133
Selection of the integrator sample rate
Table 134
EFMPLL settings information
7
6
5
4
3
2
1
0
1
0
Samplerate.1 Samplerate.0
PosErr.1
PosErr.6
PosErr.5
PosErr.4
PosErr.3
PosErr.2
PosErr.0
Samplerate.1 Samplerate.0
SAMPLE RATE
0
0
1
1
0
1
0
1
392
196
98
49
INTENDED
ENCODER SPEED
DIGITAL
MULTIPLICATION
FACTOR
ANALOG PLL
MULTIPLICATION
FACTOR
PROGRAMMABLE
DIVIDER FACTOR
POSITION ERROR
TIME CONSTANT
n = 1
n = 2
n = 4
294
147
98
4
4
4
12
6
4
2581 ms
635 ms
160 ms
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