參數(shù)資料
型號(hào)： SAA7392HL
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Channel encoder/decoder CDR60
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80
文件頁數(shù)： 59/76頁
文件大?。?/td> 246K
代理商： SAA7392HL
2000 Mar 21
59
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
7.17
The Wobble processor
The Wobble processor is a critical part of the recording
process, and performs two main functions:
To extract the ATIP data from the wobble signal
To control the linear disc speed during recording.
The Wobble processor comprises four functions, a
front-end ADC, a digital PLL, the ATIP bit detector and the
ATIP data read interface.
7.17.1
T
HE
W
OBBLE
ADC
FUNCTION
This converts the ATIP signal (WIN) to the digital domain.
7.17.2
T
HE
W
OBBLE
PLL
ThePLLhasaPItypeloopfilter.Thebandwidthoftheloop
andthe integratorareprogrammable bytheuser. The user
can also read and write the PLL frequency, the write mode
is available to aid PLL lock-in. The block outputs a pulse
signal at 44.1 kHz, which is phase modulated by the ATIP
signal.
7.17.3
T
HE
ATIP
BIT DETECTOR
This function extracts the ATIP information bits from the
ADC output and passes them to the ATIP read interface
block. It also outputs the ATIPSync pulse. In order to
protect the ATIPSyncs, a flywheel mechanism exists to
interpolate ATIPSyncs if none are detected. This is a
requirement to ensure that the recording process does not
get corrupted.
7.17.4
T
HE
ATIP
READ INTERFACE
TheATIPdataisreadbytheon-chipmicroprocessor.Data
availability can be checked by polling the ATIPReady bit in
the ATIP Status Register. The microprocessor must read
both the ATIPData and ATIPDataEnd registers in order to
complete the data read process correctly. If this does not
happen, a status bit is set to warn the microcontroller.
7.17.5
W
OBBLE
C
ONFIGURATION
R
EGISTER
1 (W
OBBLE
C
ONFIG
1)
This is a dual-function register, the specific function is determined by the state of bit 7. When bit 7 = 0, the function is as
described in Tables 135 to 138. When bit 7 = 1, the function is as described in Tables 135 and 139.
Table 135
Wobble Configuration Register 1 (address 27H) - WRITE
Table 136
Description of WobbleConfig1 bits, bit 7 = 0
7
6
5
4
3
2
1
0
0
1
0
PLLIntBW.2
PLLIntBW.1
WinWidth.4
PLLIntBW.0
WinWidth.3
LoopBW.2
WindWidth.2 WindWidth.1 WindWidth.0
LoopBW.1
LoopBW.0
ATIPhold
BIT
SYMBOL
DESCRIPTION
5
4
3
PLLIntBW.2
PLLIntBW.1
PLLIntBW.0
LoopBW<2:0>
These 3 bits select the integrator bandwidth; see Table 137.
2 to 0
These 3 bits select the loop bandwidth; see Table 138. The PLL
bandwidth is proportional to the system clock frequency and determines
the following performance points:
Loop bandwidth should be approximately equal to bit rate to get good
detector performance
Loop bandwidth depends on ATIP signal scaling. Current figures are
valid for
6 dB scaling
PLL lock-in range is approximately equal to loop bandwidth.
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