參數(shù)資料
型號(hào)： SAA7392HL
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： Channel encoder/decoder CDR60
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP80
封裝： 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80
文件頁數(shù)： 24/76頁
文件大?。?/td> 246K
代理商： SAA7392HL
2000 Mar 21
24
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
Table 33
Selection of PLL bandwidth
Table 34
Selection of low-pass bandwidth
7.5.5
PLL F
REQUENCY
P
RESET
R
EGISTER
(PLLF
REQ
)
The function of this register is dependent upon whether its being read or written. Tables 35 and 36 define the register
function for the write operation. Tables 35 and 37 define the register function for the read operation.
Table 35
PLL Frequency Preset Register (address 02H) - WRITE/READ
Table 36
Description of PLLFreq bits for write operation
Table 37
Description of PLLFreq bits for read operation
PLLBWF1.1
PLLBWF1.0
PLL BANDWIDTH
0
0
1
1
0
1
0
1
21000 Hz
10528 Hz
5264 Hz
2632 Hz
LPBWF2.1
LPBWF2.0
LOW-PASS BANDWIDTH
0
0
1
1
0
1
0
1
42100 Hz
21000 Hz
10528 Hz
This value is reserved.
7
6
5
4
3
2
1
0
PLLFreq.9
JV.7
PLLFreq.8
JV.6
PLLFreq.7
JV.5
PLLFreq.6
JV.4
PLLFreq.5
JV.3
PLLFreq.4
JV.2
PLLFreq.3
JV.1
PLLFreq.2
JV.0
BIT
SYMBOL
DESCRIPTION
7 to 0
PLLFreq<9:2> These are the 8 MSBs of the 10-bit code used to set the PLL frequency. The 2 LSBs
reside in the PLLEqu register; these 2 bits should be written to first. The PLL frequency
can be set using the following equation:
BIT
SYMBOL
DESCRIPTION
7 to 0
JV.7 to JV.0
Jitter value.
These 8 bits determine the PLL clock jitter value (jitter values below 7%
cannot be measured with this register). The absolute clock jitter value can be calculated
as follows:
f
PLL
PLL512
2
5
–
+
f
clk
×
=
PLL clock recovery jitter %
JV<7:0>
6.5
–
2048
100
×
=
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