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參數(shù)資料
| 型號(hào)： | SAA7392HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | Channel encoder/decoder CDR60 |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁數(shù)： | 22/76頁 |
| 文件大?。?/td> | 246K |
| 代理商： | SAA7392HL |
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2000 Mar 21
22
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
7.5.3
PLL L
OCK
S
ELECT
R
EGISTER
(PLLL
OCK
)
The behaviour of this register is dependent upon whether its being read or written. The behaviour for the write operation
is described in Tables 24 to 27. When read the 8 MSBs of the PLL frequency counter are returned; this is described in
Tables 24 and 28.
Table 24
PLL Lock Select Register (address 00H) - WRITE/READ
Table 25
Description of PLLLock bits for write operation
Table 26
Selection of phase override setting
Table 27
Selection of PLL lock
7
6
5
4
3
2
1
0
LockOride
PLLFreq.7
PhaOset.2
PLLFreq.6
PhaOset.1
PLLFreq.5
PhaOset.0
PLLFreq.4
PLLForceL.3 PLLForceL.2 PLLForceL.1 PLLForceL.0
PLLFreq.3
PLLFreq.2
PLLFreq.1
PLLFreq.0
BIT
SYMBOL
DESCRIPTION
7
LockOride
When LockOride = 0, then automatic lock behaviour selected, PLLForceL<3:0> must be
set to ‘0000’. When LockOride = 1, then PLL manual override, PLLForceL<3:0> must
also be programmed.
These 3 bits are used to select the phase override settings; see Table 26.
6
5
4
3
2
1
0
PhaOset.2
PhaOset.1
PhaOset.0
PLLForceL.3 These 4 bits are used to select the PLL lock; see Table 27.
PLLForceL.2
PLLForceL.1
PLLForceL.0
PhaOset.2
PhaOset.1
PhaOset.0
PHASE OVERRIDE
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
reserved
3
/
8
×
PLL clock over-equalized T3
2
/
8
×
PLL clock over-equalized T3
1
/
8
×
PLL clock over-equalized T3
correct equalisation
1
/
8
×
PLL clock under-equalized T3
2
/
8
×
PLL clock under-equalized T3
3
/
8
×
PLL clock under-equalized T3
PLLForceL.3 PLLForceL.2 PLLForceL.1 PLLForceL.0
PLL LOCK
0
0
0
0
1
0
0
1
1
0
0
0
0
1
0
0
1
0
0
0
automatic lock behaviour
force PLL in-lock
force PLL into outer-lock
force PLL into inner-lock
force PLL into Hold mode (PLL frequency can be
forced using preset value in register PLLFreq)
all other combinations are reserved
X
X
X
X
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