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參數(shù)資料
| 型號： | SAA7392HL |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 消費家電 |
| 英文描述： | Channel encoder/decoder CDR60 |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP80 |
| 封裝： | 12 X 12 MM, 1.40 MM HEIGHT, PLASTIC, MS-026, SOT-315-1, LQFP-80 |
| 文件頁數(shù)： | 30/76頁 |
| 文件大?。?/td> | 246K |
| 代理商： | SAA7392HL |
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2000 Mar 21
30
Philips Semiconductors
Preliminary specification
Channel encoder/decoder CDR60
SAA7392
7.6.5
D
ATA
FIFO
The decoder block can be viewed as a FIFO, demodulated
data is written in while the output interface reads from it.
The way in which the FIFO is filled depends on the
decoder mode set via register DecoMode. The decoder
modes that effect the filling of the FIFO are described in
Sections 7.6.5.1 to 7.6.5.3.
Data is read out via the output interface and is only
possible if enough data is present in the FIFO. The
minimumamountofdatais110 C1 frames(C1 frame = 24
user bytes).
7.6.5.1
Flush mode
The FIFO content is thrown away; no read-out possible. It
is necessary to flush the FIFO every time a context switch
is made; when data written to the FIFO is not subsequent
with data already present in the FIFO.
7.6.5.2
Hold mode
Writing to the FIFO is stopped; read-out possible if FIFO
wasfilled.ThismodeisintendedtoavoidFIFOoverflowby
implementing a ‘stop write - jump back’ action in the
microprocessor. When the microprocessor switches to
hold mode the switch-over is synchronised internally with
the next subcode block start, allowing the microprocessor
to know exactly where the writing will stop or start. This
mode is also intended to avoid overflow in the block
decoder; on imminent overflow the microprocessor can
switch to hold mode. When it jumps back one track and
switches off hold mode on the same subcode address the
SAA7392 will make a seamless link.
7.6.5.3
Play mode
The FIFO is filled; read-out possible when FIFO filling big
enough.
7.6.5.4
Data FIFO monitoring
The state of the internal data FIFO may be monitored by
reading the AnaSet1 register. This gives the number of
C1 frames present in the FIFO including those frames in
the outer corrector (i.e. 110 in CD fast and 220 in
CD normal). One C1 frame equates to 24 user bytes in
CD mode).
7.7
Subcode interface
Q-channel subcode data can be read using the ClockPre
and DecoMode registers. The ClockPre register must be
read first; this contains the status of the Q-channel
subcode that may be read. Reading the ClockPre register
with Ready = 1 will block the subcode interface for data
read; no new subcode will overwrite the current subcode,
and the microprocessor may retrieve as many bytes (up
to 12) as required by issuing reads to register DecoMode.
After finishing the subcode read the microprocessor must
release the interface by issuing a read to the dummy
register SubReadEnd (no data can be read from it); this
allows the SAA7392 to capture new subcode frames.
The serial Q to W subcode is output on the V4 pin as
illustrated in Fig.10. The subcode sync word is formed by
a pause of
200
/
n
μ
s minimum; where n = the disc speed.
Each subcode word starts with a logic 1 followed by 7 bits
(Q to W); the bit time is 0.5 of the period of the WCLK
signal, (
11.3
/
n
μ
s). The gap between the words is between
11.3
/
n
and
90
/
n
μ
s. Note that the subcode data cannot be
guaranteed at a rate higher than 0.5
×
the maximum data
rate programmed.
The subcode data is also available in the EBU output
(EBUOUT).
Fig.10 Subcode format and timing on V4 pin.
handbook, full pagewidth
MGR799
W96
200/n
μ
s min
11.3/n
μ
s
11.3/n
μ
s min
90/n
μ
s max
1
Q1
R1
S1
T
U1
V
W1
1
Q2
n = disc speed
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