
64
05/08/00
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456
12345678901234567890123456789012123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456
13.2.41 Config Register 1 or 2: Non-Posted Memory Base Register (read/write, bit 15-0; offset 70h)
This register defines the base address of the non-posted memory-mapped address range for forwarding the cycle through
the bridge. Upper twelve bits corresponding to address bits [31:20] are read/write. Lower 20 bits (19:0) are assumed to
be 00000h.
PI7C7100
3-Port PCI Bridge
ADVANCE INFORMATION
13.2.42 Config Register 1 or 2: Non-Posted Memory Limit Register (read/write, bit 31-16; offset 70h)
This register defines the upper limit address of the non-posted memory-mapped address range for forwarding the cycle
through the bridge. Upper twelve bits corresponding to address bits [31:20] are read/write. Lower 20 bits (19:0) are assumed
to be FFFFFh.
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13.2.43 Configuration Register 1: Port Option Register (bit 15-0; offset74h)