- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄368020 > PI7C7100BNA PCI Bus Interface/Controller PDF資料下載
參數(shù)資料
| 型號： | PI7C7100BNA |
| 英文描述： | PCI Bus Interface/Controller |
| 中文描述： | PCI總線接口/控制器 |
| 文件頁數(shù)： | 43/118頁 |
| 文件大小： | 2962K |
| 代理商： | PI7C7100BNA |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁當前第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁第98頁第99頁第100頁第101頁第102頁第103頁第104頁第105頁第106頁第107頁第108頁第109頁第110頁第111頁第112頁第113頁第114頁第115頁第116頁第117頁第118頁
35
05/08/00
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567
123456789012345678901234567890121234567890123456789012345678901212345678901234567890123456789012123456789012345678901234567890121234567
PI7C7100
ADVANCE INFORMATION
For upstream transactions, when the parity error is being passed back from the target bus and the parity error condition
was not originally detected on the initiator bus, the following events occur:
PI7C7100 asserts S_PERR# two cycles after the data transfer, if the following are both true:
- The parity error response bit is set in the command register of the primary interface.
- The parity error response bit is set in the bridge control register of the secondary interface.
PI7C7100 completes the transaction normally.
7.2.4 Posted Write Transactions
During downstream posted write transactions, when PI7C7100 responds as a target, it detects a data parity error on the
initiator (primary) bus, the following events occur:
PI7C7100 asserts P_PERR# two cycles after the data transfer, if the parity error response bit is set in the
command register of primary interface.
PI7C7100 sets the parity error detected bit in the status register of the primary interface.
PI7C7100 captures and forwards the bad parity condition to the secondary bus.
PI7C7100 completes the transaction normally.
Similarly, during upstream posted write transactions, when PI7C7100 responds as a target, it detects a data parity error
on the initiator (secondary) bus, the following events occur:
PI7C7100 asserts S_PERR# two cycles after the data transfer, if the parity error response bit is set in the bridge
control register of the secondary interface.
PI7C7100 sets the parity error detected bit in the status register of the secondary interface.
PI7C7100 captures and forwards the bad parity condition to the primary bus.
PI7C7100 completes the transaction normally.
During downstream write transactions, when a data parity error is reported on the target (secondary) bus by the targets
assertion of S_PERR#, the following events occur:
PI7C7100 sets the data parity detected bit in the status register of secondary interface, if the parity error
response bit is set in the bridge control register of the secondary interface.
PI7C7100 asserts P_SERR# and sets the signaled system error bit in the status register, if all the following
conditions are met:
- The SERR# enable bit is set in the command register.
- The posted write parity error bit of P_SERR# event disable register is not set.
- The parity error response bit is set in the bridge control register of the secondary interface.
- The parity error response bit is set in the command register of the primary interface.
- PI7C7100 has not detected the parity error on the primary (initiator) bus which the parity error is not forwarded
from the primary bus to the secondary bus.
During upstream write transactions, when a data parity error is reported on the target (primary) bus by the targets assertion
of P_PERR#, the following events occur:
PI7C7100 sets the data parity detected bit in the status register, if the parity error response bit is set in the
command register of the primary interface.
PI7C7100 asserts P_SERR# and sets the signaled system error bit in the status register, if all the following
conditions are met:
- The SERR# enable bit is set in the command register.
- The parity error response bit is set in the bridge control register of the secondary interface.
- The parity error response bit is set in the command register of the primary interface.
- PI7C7100 has not detected the parity error on the secondary (initiator) bus which the parity error is not
forwarded from the secondary bus to the primary bus.
Assertion of P_SERR# is used to signal the parity error condition when the initiator does not know that the error occurred.
相關PDF資料 |
PDF描述 |
|---|---|
| PI7C7100 | 3-Port PCI Bridge |
| PI7C7100CNA | 3-Port PCI Bridge |
| PI7C7300 | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 3-PORT PCI-to-PCI BRIDGE |
| PI7C7300ANA | 3-PORT PCI-to-PCI BRIDGE |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C7100CNA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-Port PCI Bridge |
| PI7C7300 | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:3-PORT PCI-to-PCI BRIDGE |
| PI7C7300AEVB-3 | 功能描述:界面開發(fā)工具 3 Port PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C7300ANA | 制造商:Pericom Semiconductor Corporation 功能描述:PCI-to-PCI Bridge 272-Pin BGA 制造商:Pericom Semiconductor Corporation 功能描述:PCI to PCI Bridge 272-Pin BGA |
發(fā)布緊急采購，3分鐘左右您將得到回復。